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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Driver parameters
*
*******************************************************************/
#define STDIN_BASEADDRESS 0x40600000
#define STDOUT_BASEADDRESS 0x40600000
/******************************************************************/
/* Definitions for driver PLBARB */
#define XPAR_XPLBARB_NUM_INSTANCES 1
/* Definitions for peripheral PLB */
#define XPAR_PLB_BASEADDR 0x00000000
#define XPAR_PLB_HIGHADDR 0x00000000
#define XPAR_PLB_DEVICE_ID 0
#define XPAR_PLB_PLB_NUM_MASTERS 3
/******************************************************************/
/* Definitions for driver OPBARB */
#define XPAR_XOPBARB_NUM_INSTANCES 1
/* Definitions for peripheral OPB */
#define XPAR_OPB_BASEADDR 0xFFFFFFFF
#define XPAR_OPB_HIGHADDR 0x00000000
#define XPAR_OPB_DEVICE_ID 0
#define XPAR_OPB_NUM_MASTERS 1
/******************************************************************/
/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1
/* Definitions for peripheral CONSOLE */
#define XPAR_CONSOLE_BASEADDR 0x40600000
#define XPAR_CONSOLE_HIGHADDR 0x4060FFFF
#define XPAR_CONSOLE_DEVICE_ID 0
#define XPAR_CONSOLE_BAUDRATE 115200
#define XPAR_CONSOLE_USE_PARITY 0
#define XPAR_CONSOLE_ODD_PARITY 0
#define XPAR_CONSOLE_DATA_BITS 8
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 3
/* Definitions for peripheral LEDS */
#define XPAR_LEDS_BASEADDR 0x40000000
#define XPAR_LEDS_HIGHADDR 0x4000FFFF
#define XPAR_LEDS_DEVICE_ID 0
#define XPAR_LEDS_INTERRUPT_PRESENT 0
#define XPAR_LEDS_IS_DUAL 0
/* Definitions for peripheral PBLEDS */
#define XPAR_PBLEDS_BASEADDR 0x40020000
#define XPAR_PBLEDS_HIGHADDR 0x4002FFFF
#define XPAR_PBLEDS_DEVICE_ID 1
#define XPAR_PBLEDS_INTERRUPT_PRESENT 0
#define XPAR_PBLEDS_IS_DUAL 0
/* Definitions for peripheral PUSHBUTTONS */
#define XPAR_PUSHBUTTONS_BASEADDR 0x40040000
#define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF
#define XPAR_PUSHBUTTONS_DEVICE_ID 2
#define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1
#define XPAR_PUSHBUTTONS_IS_DUAL 0
/******************************************************************/
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1
/* Definitions for peripheral OPBTIMER */
#define XPAR_OPBTIMER_BASEADDR 0x41C00000
#define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF
#define XPAR_OPBTIMER_DEVICE_ID 0
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral INTC */
#define XPAR_INTC_BASEADDR 0x41200000
#define XPAR_INTC_HIGHADDR 0x4120FFFF
#define XPAR_INTC_DEVICE_ID 0
#define XPAR_INTC_KIND_OF_INTR 0x00000000
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID
#define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001
#define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0
#define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002
#define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1
#define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004
#define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2
/******************************************************************/
/* Definitions for driver DDR */
#define XPAR_XDDR_NUM_INSTANCES 1
/* Definitions for peripheral DDR_SDRAM_64MX32 */
#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF
#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000
#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0
#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0
/******************************************************************/
/* Definitions for peripheral DDR_SDRAM_64MX32 */
#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000
#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF
/******************************************************************/
/* Definitions for peripheral HARD_TEMAC_0 */
#define XPAR_HARD_TEMAC_0_PHY_TYPE 1
/******************************************************************/
/* Definitions for driver TEMAC */
#define XPAR_XTEMAC_NUM_INSTANCES 1
/* Definitions for peripheral ETHERNET */
#define XPAR_ETHERNET_DEVICE_ID 0
#define XPAR_ETHERNET_BASEADDR 0x81200000
#define XPAR_ETHERNET_HIGHADDR 0x8120FFFF
#define XPAR_ETHERNET_RXFIFO_DEPTH 32768
#define XPAR_ETHERNET_TXFIFO_DEPTH 32768
#define XPAR_ETHERNET_MAC_FIFO_DEPTH 64
#define XPAR_ETHERNET_DMA_TYPE 1
#define XPAR_ETHERNET_TX_DRE_TYPE 0
#define XPAR_ETHERNET_RX_DRE_TYPE 0
#define XPAR_ETHERNET_INCLUDE_TX_CSUM 0
#define XPAR_ETHERNET_INCLUDE_RX_CSUM 0
/******************************************************************/
/* Definitions for peripheral FLASH */
#define XPAR_FLASH_NUM_BANKS_MEM 1
/******************************************************************/
/* Definitions for peripheral FLASH */
#define XPAR_FLASH_MEM0_BASEADDR 0x06000000
#define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF
/******************************************************************/
/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000
#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff
/******************************************************************/
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
/******************************************************************/
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