/* The header file is generated by make_header.py from VIM.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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*/
#ifndef LIBBSP_ARM_tms570_VIM
#define LIBBSP_ARM_tms570_VIM
#include <bsp/utility.h>
typedef struct{
uint32_t PARFLG; /*Interrupt Vector Table Parity Flag Register*/
uint32_t PARCTL; /*Interrupt Vector Table Parity Control Register*/
uint32_t ADDERR; /*Address Parity Error Register*/
uint32_t FBPARERR; /*Fall-Back Address Parity Error Register*/
uint8_t reserved1 [4];
uint32_t IRQINDEX; /*IRQ Index Offset Vector Register*/
uint32_t FIQINDEX; /*FIQ Index Offset Vector Register*/
uint8_t reserved2 [8];
uint32_t FIRQPR[3]; /*FIQ/IRQ Program Control Register*/
uint8_t reserved3 [4];
uint32_t INTREQ[3]; /*Pending Interrupt Read Location Register*/
uint8_t reserved4 [4];
uint32_t REQENASET[3]; /*Interrupt Enable Set Register */
uint8_t reserved5 [4];
uint32_t REQENACLR[3]; /*Interrupt Enable Clear Register */
uint8_t reserved6 [4];
uint32_t WAKEENASET[3]; /*Wake-Up Enable Set Register*/
uint8_t reserved7 [4];
uint32_t WAKEENACLR[3]; /*Wake-Up Enable Clear Registers*/
uint8_t reserved8 [4];
uint32_t IRQVECREG; /*IRQ Interrupt Vector Register*/
uint32_t FIQVECREG; /*FIQ Interrupt Vector Register*/
uint32_t CAPEVT; /*Capture Event Register*/
uint8_t reserved9 [4];
uint32_t CHANCTRL[24]; /*VIM Interrupt Control Register*/
} tms570_vim_t;
/*----------------------TMS570_VIMPARFLG----------------------*/
/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
#define TMS570_VIM_PARFLG_PARFLG BSP_FLD32(0)
/*----------------------TMS570_VIMPARCTL----------------------*/
/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
#define TMS570_VIM_PARCTL_TEST BSP_FLD32(8)
/* field: PARENA - VIM parity enable. */
#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
#define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*----------------------TMS570_VIMADDERR----------------------*/
/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31)
/* field: ADDERR - Address parity error register. */
#define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8)
#define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8)
#define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8)
/* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */
#define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1)
#define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_VIMFBPARERR---------------------*/
/* field: FBPARERR - Fall back address parity error. */
#define TMS570_VIM_FBPARERR_FBPARERR(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_FBPARERR_FBPARERR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_FBPARERR_FBPARERR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_VIMIRQINDEX---------------------*/
/* field: IRQINDEX - IRQ index vector. */
#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*---------------------TMS570_VIMFIQINDEX---------------------*/
/* field: FIQINDEX - FIQ index offset vector. */
#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_VIMFIRQPR----------------------*/
/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
#define TMS570_VIM_FIRQPR_FIRQPRx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_FIRQPR_FIRQPRx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_FIRQPR_FIRQPRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_VIMINTREQ----------------------*/
/* field: INTREQx - Pending interrupt bits. 96 bit register. */
#define TMS570_VIM_INTREQ_INTREQx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_INTREQ_INTREQx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_INTREQ_INTREQx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMREQENASET--------------------*/
/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
#define TMS570_VIM_REQENASET_REQENASETx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_REQENASET_REQENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_REQENASET_REQENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMREQENACLR--------------------*/
/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
#define TMS570_VIM_REQENACLR_REQENACLRx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_REQENACLR_REQENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_REQENACLR_REQENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMWAKEENASET--------------------*/
/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
#define TMS570_VIM_WAKEENASET_WAKEENASETx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_WAKEENASET_WAKEENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_WAKEENASET_WAKEENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMWAKEENACLR--------------------*/
/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
#define TMS570_VIM_WAKEENACLR_WAKEENACLRx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMIRQVECREG--------------------*/
/* field: IRQVECREG - IRQ interrupt vector register. */
#define TMS570_VIM_IRQVECREG_IRQVECREG(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_IRQVECREG_IRQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_IRQVECREG_IRQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMFIQVECREG--------------------*/
/* field: FIQVECREG - FIQ interrupt vector register. */
#define TMS570_VIM_FIQVECREG_FIQVECREG(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_FIQVECREG_FIQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_FIQVECREG_FIQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_VIMCAPEVT----------------------*/
/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
#define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
/* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */
#define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6)
#define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
/*---------------------TMS570_VIMCHANCTRL---------------------*/
/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
#define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
/* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22)
#define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22)
#define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
/* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14)
#define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14)
#define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
/* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6)
#define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
#endif /* LIBBSP_ARM_tms570_VIM */
