From bceabc95c1c85d793200446fa85f1ddc6313ea29 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 9 Oct 2013 22:42:09 +0200 Subject: Move files to match FreeBSD layout --- freebsd/sys/arm/arm/in_cksum.c | 154 ++++++ freebsd/sys/arm/include/machine/cpufunc.h | 618 +++++++++++++++++++++++ freebsd/sys/arm/include/machine/in_cksum.h | 66 +++ freebsd/sys/arm/include/machine/legacyvar.h | 57 +++ freebsd/sys/arm/include/machine/pci_cfgreg.h | 52 ++ freebsd/sys/arm/pci/pci_bus.c | 729 +++++++++++++++++++++++++++ 6 files changed, 1676 insertions(+) create mode 100644 freebsd/sys/arm/arm/in_cksum.c create mode 100644 freebsd/sys/arm/include/machine/cpufunc.h create mode 100644 freebsd/sys/arm/include/machine/in_cksum.h create mode 100644 freebsd/sys/arm/include/machine/legacyvar.h create mode 100644 freebsd/sys/arm/include/machine/pci_cfgreg.h create mode 100644 freebsd/sys/arm/pci/pci_bus.c (limited to 'freebsd/sys/arm') diff --git a/freebsd/sys/arm/arm/in_cksum.c b/freebsd/sys/arm/arm/in_cksum.c new file mode 100644 index 00000000..db98915d --- /dev/null +++ b/freebsd/sys/arm/arm/in_cksum.c @@ -0,0 +1,154 @@ +#include + +/* $NetBSD: in_cksum.c,v 1.7 1997/09/02 13:18:15 thorpej Exp $ */ + +/*- + * Copyright (c) 1988, 1992, 1993 + * The Regents of the University of California. All rights reserved. + * Copyright (c) 1996 + * Matt Thomas + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)in_cksum.c 8.1 (Berkeley) 6/10/93 + */ + +#include /* RCS ID & Copyright macro defns */ +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +/* + * Checksum routine for Internet Protocol family headers + * (Portable Alpha version). + * + * This routine is very heavily used in the network + * code and should be modified for each CPU to be as fast as possible. + */ + +#define ADDCARRY(x) (x > 65535 ? x -= 65535 : x) +#define REDUCE32 \ + { \ + q_util.q = sum; \ + sum = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \ + } +#define REDUCE16 \ + { \ + q_util.q = sum; \ + l_util.l = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \ + sum = l_util.s[0] + l_util.s[1]; \ + ADDCARRY(sum); \ + } + +union l_util { + u_int16_t s[2]; + u_int32_t l; +}; +union q_util { + u_int16_t s[4]; + u_int32_t l[2]; + u_int64_t q; +}; + +u_short +in_addword(u_short a, u_short b) +{ + u_int64_t sum = a + b; + + ADDCARRY(sum); + return (sum); +} + +static +uint64_t _do_cksum(void *addr, int len) +{ + uint64_t sum; + union q_util q_util; + + sum = do_cksum(addr, len); + REDUCE32; + return (sum); +} + +u_short +in_cksum_skip(struct mbuf *m, int len, int skip) +{ + u_int64_t sum = 0; + int mlen = 0; + int clen = 0; + caddr_t addr; + union q_util q_util; + union l_util l_util; + + len -= skip; + for (; skip && m; m = m->m_next) { + if (m->m_len > skip) { + mlen = m->m_len - skip; + addr = mtod(m, caddr_t) + skip; + goto skip_start; + } else { + skip -= m->m_len; + } + } + + for (; m && len; m = m->m_next) { + if (m->m_len == 0) + continue; + mlen = m->m_len; + addr = mtod(m, caddr_t); +skip_start: + if (len < mlen) + mlen = len; + + if ((clen ^ (int) addr) & 1) + sum += _do_cksum(addr, mlen) << 8; + else + sum += _do_cksum(addr, mlen); + + clen += mlen; + len -= mlen; + } + REDUCE16; + return (~sum & 0xffff); +} + +u_int in_cksum_hdr(const struct ip *ip) +{ + u_int64_t sum = do_cksum(ip, sizeof(struct ip)); + union q_util q_util; + union l_util l_util; + REDUCE16; + return (~sum & 0xffff); +} diff --git a/freebsd/sys/arm/include/machine/cpufunc.h b/freebsd/sys/arm/include/machine/cpufunc.h new file mode 100644 index 00000000..822fadb1 --- /dev/null +++ b/freebsd/sys/arm/include/machine/cpufunc.h @@ -0,0 +1,618 @@ +/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ + +/*- + * Copyright (c) 1997 Mark Brinicombe. + * Copyright (c) 1997 Causality Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Causality Limited. + * 4. The name of Causality Limited may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * cpufunc.h + * + * Prototypes for cpu, mmu and tlb related functions. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_CPUFUNC_HH_ +#define _MACHINE_CPUFUNC_HH_ + +#ifdef _KERNEL + +#include +#include +#include /* For in[bwl] and out[bwl] */ + +static __inline void +breakpoint(void) +{ + __asm(".word 0xe7ffffff"); +} + +struct cpu_functions { + + /* CPU functions */ + + u_int (*cf_id) (void); + void (*cf_cpwait) (void); + + /* MMU functions */ + + u_int (*cf_control) (u_int bic, u_int eor); + void (*cf_domains) (u_int domains); + void (*cf_setttb) (u_int ttb); + u_int (*cf_faultstatus) (void); + u_int (*cf_faultaddress) (void); + + /* TLB functions */ + + void (*cf_tlb_flushID) (void); + void (*cf_tlb_flushID_SE) (u_int va); + void (*cf_tlb_flushI) (void); + void (*cf_tlb_flushI_SE) (u_int va); + void (*cf_tlb_flushD) (void); + void (*cf_tlb_flushD_SE) (u_int va); + + /* + * Cache operations: + * + * We define the following primitives: + * + * icache_sync_all Synchronize I-cache + * icache_sync_range Synchronize I-cache range + * + * dcache_wbinv_all Write-back and Invalidate D-cache + * dcache_wbinv_range Write-back and Invalidate D-cache range + * dcache_inv_range Invalidate D-cache range + * dcache_wb_range Write-back D-cache range + * + * idcache_wbinv_all Write-back and Invalidate D-cache, + * Invalidate I-cache + * idcache_wbinv_range Write-back and Invalidate D-cache, + * Invalidate I-cache range + * + * Note that the ARM term for "write-back" is "clean". We use + * the term "write-back" since it's a more common way to describe + * the operation. + * + * There are some rules that must be followed: + * + * I-cache Synch (all or range): + * The goal is to synchronize the instruction stream, + * so you may beed to write-back dirty D-cache blocks + * first. If a range is requested, and you can't + * synchronize just a range, you have to hit the whole + * thing. + * + * D-cache Write-Back and Invalidate range: + * If you can't WB-Inv a range, you must WB-Inv the + * entire D-cache. + * + * D-cache Invalidate: + * If you can't Inv the D-cache, you must Write-Back + * and Invalidate. Code that uses this operation + * MUST NOT assume that the D-cache will not be written + * back to memory. + * + * D-cache Write-Back: + * If you can't Write-back without doing an Inv, + * that's fine. Then treat this as a WB-Inv. + * Skipping the invalidate is merely an optimization. + * + * All operations: + * Valid virtual addresses must be passed to each + * cache operation. + */ + void (*cf_icache_sync_all) (void); + void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); + + void (*cf_dcache_wbinv_all) (void); + void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); + void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); + void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); + + void (*cf_idcache_wbinv_all) (void); + void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); + void (*cf_l2cache_wbinv_all) (void); + void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); + void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); + void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); + + /* Other functions */ + + void (*cf_flush_prefetchbuf) (void); + void (*cf_drain_writebuf) (void); + void (*cf_flush_brnchtgt_C) (void); + void (*cf_flush_brnchtgt_E) (u_int va); + + void (*cf_sleep) (int mode); + + /* Soft functions */ + + int (*cf_dataabt_fixup) (void *arg); + int (*cf_prefetchabt_fixup) (void *arg); + + void (*cf_context_switch) (void); + + void (*cf_setup) (char *string); +}; + +extern struct cpu_functions cpufuncs; +extern u_int cputype; + +#define cpu_id() cpufuncs.cf_id() +#define cpu_cpwait() cpufuncs.cf_cpwait() + +#define cpu_control(c, e) cpufuncs.cf_control(c, e) +#define cpu_domains(d) cpufuncs.cf_domains(d) +#define cpu_setttb(t) cpufuncs.cf_setttb(t) +#define cpu_faultstatus() cpufuncs.cf_faultstatus() +#define cpu_faultaddress() cpufuncs.cf_faultaddress() + +#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() +#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) +#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() +#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) +#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() +#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) + +#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() +#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) + +#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() +#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) +#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) +#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) + +#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() +#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) +#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() +#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) +#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) +#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) + +#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() +#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() +#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() +#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) + +#define cpu_sleep(m) cpufuncs.cf_sleep(m) + +#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) +#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) +#define ABORT_FIXUP_OK 0 /* fixup succeeded */ +#define ABORT_FIXUP_FAILED 1 /* fixup failed */ +#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ + +#define cpu_setup(a) cpufuncs.cf_setup(a) + +int set_cpufuncs (void); +#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ +#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ + +void cpufunc_nullop (void); +int cpufunc_null_fixup (void *); +int early_abort_fixup (void *); +int late_abort_fixup (void *); +u_int cpufunc_id (void); +u_int cpufunc_control (u_int clear, u_int bic); +void cpufunc_domains (u_int domains); +u_int cpufunc_faultstatus (void); +u_int cpufunc_faultaddress (void); + +#ifdef CPU_ARM3 +u_int arm3_control (u_int clear, u_int bic); +void arm3_cache_flush (void); +#endif /* CPU_ARM3 */ + +#if defined(CPU_ARM6) || defined(CPU_ARM7) +void arm67_setttb (u_int ttb); +void arm67_tlb_flush (void); +void arm67_tlb_purge (u_int va); +void arm67_cache_flush (void); +void arm67_context_switch (void); +#endif /* CPU_ARM6 || CPU_ARM7 */ + +#ifdef CPU_ARM6 +void arm6_setup (char *string); +#endif /* CPU_ARM6 */ + +#ifdef CPU_ARM7 +void arm7_setup (char *string); +#endif /* CPU_ARM7 */ + +#ifdef CPU_ARM7TDMI +int arm7_dataabt_fixup (void *arg); +void arm7tdmi_setup (char *string); +void arm7tdmi_setttb (u_int ttb); +void arm7tdmi_tlb_flushID (void); +void arm7tdmi_tlb_flushID_SE (u_int va); +void arm7tdmi_cache_flushID (void); +void arm7tdmi_context_switch (void); +#endif /* CPU_ARM7TDMI */ + +#ifdef CPU_ARM8 +void arm8_setttb (u_int ttb); +void arm8_tlb_flushID (void); +void arm8_tlb_flushID_SE (u_int va); +void arm8_cache_flushID (void); +void arm8_cache_flushID_E (u_int entry); +void arm8_cache_cleanID (void); +void arm8_cache_cleanID_E (u_int entry); +void arm8_cache_purgeID (void); +void arm8_cache_purgeID_E (u_int entry); + +void arm8_cache_syncI (void); +void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); +void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); +void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); +void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); +void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); + +void arm8_context_switch (void); + +void arm8_setup (char *string); + +u_int arm8_clock_config (u_int, u_int); +#endif + +#ifdef CPU_SA110 +void sa110_setup (char *string); +void sa110_context_switch (void); +#endif /* CPU_SA110 */ + +#if defined(CPU_SA1100) || defined(CPU_SA1110) +void sa11x0_drain_readbuf (void); + +void sa11x0_context_switch (void); +void sa11x0_cpu_sleep (int mode); + +void sa11x0_setup (char *string); +#endif + +#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) +void sa1_setttb (u_int ttb); + +void sa1_tlb_flushID_SE (u_int va); + +void sa1_cache_flushID (void); +void sa1_cache_flushI (void); +void sa1_cache_flushD (void); +void sa1_cache_flushD_SE (u_int entry); + +void sa1_cache_cleanID (void); +void sa1_cache_cleanD (void); +void sa1_cache_cleanD_E (u_int entry); + +void sa1_cache_purgeID (void); +void sa1_cache_purgeID_E (u_int entry); +void sa1_cache_purgeD (void); +void sa1_cache_purgeD_E (u_int entry); + +void sa1_cache_syncI (void); +void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); +void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); +void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); +void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); +void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); + +#endif + +#ifdef CPU_ARM9 +void arm9_setttb (u_int); + +void arm9_tlb_flushID_SE (u_int va); + +void arm9_icache_sync_all (void); +void arm9_icache_sync_range (vm_offset_t, vm_size_t); + +void arm9_dcache_wbinv_all (void); +void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); +void arm9_dcache_inv_range (vm_offset_t, vm_size_t); +void arm9_dcache_wb_range (vm_offset_t, vm_size_t); + +void arm9_idcache_wbinv_all (void); +void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); + +void arm9_context_switch (void); + +void arm9_setup (char *string); + +extern unsigned arm9_dcache_sets_max; +extern unsigned arm9_dcache_sets_inc; +extern unsigned arm9_dcache_index_max; +extern unsigned arm9_dcache_index_inc; +#endif + +#if defined(CPU_ARM9E) || defined(CPU_ARM10) +void arm10_setttb (u_int); + +void arm10_tlb_flushID_SE (u_int); +void arm10_tlb_flushI_SE (u_int); + +void arm10_icache_sync_all (void); +void arm10_icache_sync_range (vm_offset_t, vm_size_t); + +void arm10_dcache_wbinv_all (void); +void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); +void arm10_dcache_inv_range (vm_offset_t, vm_size_t); +void arm10_dcache_wb_range (vm_offset_t, vm_size_t); + +void arm10_idcache_wbinv_all (void); +void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); + +void arm10_context_switch (void); + +void arm10_setup (char *string); + +extern unsigned arm10_dcache_sets_max; +extern unsigned arm10_dcache_sets_inc; +extern unsigned arm10_dcache_index_max; +extern unsigned arm10_dcache_index_inc; + +u_int sheeva_control_ext (u_int, u_int); +void sheeva_setttb (u_int); +void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); +void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); +void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); +void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); + +void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_wbinv_all (void); +#endif + +#ifdef CPU_ARM11 +void arm11_setttb (u_int); + +void arm11_tlb_flushID_SE (u_int); +void arm11_tlb_flushI_SE (u_int); + +void arm11_context_switch (void); + +void arm11_setup (char *string); +void arm11_tlb_flushID (void); +void arm11_tlb_flushI (void); +void arm11_tlb_flushD (void); +void arm11_tlb_flushD_SE (u_int va); + +void arm11_drain_writebuf (void); +#endif + +#if defined(CPU_ARM9E) || defined (CPU_ARM10) +void armv5_ec_setttb(u_int); + +void armv5_ec_icache_sync_all(void); +void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); + +void armv5_ec_dcache_wbinv_all(void); +void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); +void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); +void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); + +void armv5_ec_idcache_wbinv_all(void); +void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); +#endif + +#if defined (CPU_ARM10) || defined (CPU_ARM11) +void armv5_setttb(u_int); + +void armv5_icache_sync_all(void); +void armv5_icache_sync_range(vm_offset_t, vm_size_t); + +void armv5_dcache_wbinv_all(void); +void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); +void armv5_dcache_inv_range(vm_offset_t, vm_size_t); +void armv5_dcache_wb_range(vm_offset_t, vm_size_t); + +void armv5_idcache_wbinv_all(void); +void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); + +extern unsigned armv5_dcache_sets_max; +extern unsigned armv5_dcache_sets_inc; +extern unsigned armv5_dcache_index_max; +extern unsigned armv5_dcache_index_inc; +#endif + +#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ + defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ + defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) + +void armv4_tlb_flushID (void); +void armv4_tlb_flushI (void); +void armv4_tlb_flushD (void); +void armv4_tlb_flushD_SE (u_int va); + +void armv4_drain_writebuf (void); +#endif + +#if defined(CPU_IXP12X0) +void ixp12x0_drain_readbuf (void); +void ixp12x0_context_switch (void); +void ixp12x0_setup (char *string); +#endif + +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) +void xscale_cpwait (void); + +void xscale_cpu_sleep (int mode); + +u_int xscale_control (u_int clear, u_int bic); + +void xscale_setttb (u_int ttb); + +void xscale_tlb_flushID_SE (u_int va); + +void xscale_cache_flushID (void); +void xscale_cache_flushI (void); +void xscale_cache_flushD (void); +void xscale_cache_flushD_SE (u_int entry); + +void xscale_cache_cleanID (void); +void xscale_cache_cleanD (void); +void xscale_cache_cleanD_E (u_int entry); + +void xscale_cache_clean_minidata (void); + +void xscale_cache_purgeID (void); +void xscale_cache_purgeID_E (u_int entry); +void xscale_cache_purgeD (void); +void xscale_cache_purgeD_E (u_int entry); + +void xscale_cache_syncI (void); +void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); +void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); +void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); +void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); +void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); +void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); + +void xscale_context_switch (void); + +void xscale_setup (char *string); +#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 + CPU_XSCALE_80219 */ + +#ifdef CPU_XSCALE_81342 + +void xscalec3_l2cache_purge (void); +void xscalec3_cache_purgeID (void); +void xscalec3_cache_purgeD (void); +void xscalec3_cache_cleanID (void); +void xscalec3_cache_cleanD (void); +void xscalec3_cache_syncI (void); + +void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); +void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); +void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); +void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); +void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); + +void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); +void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); +void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); + + +void xscalec3_setttb (u_int ttb); +void xscalec3_context_switch (void); + +#endif /* CPU_XSCALE_81342 */ + +#define tlb_flush cpu_tlb_flushID +#define setttb cpu_setttb +#define drain_writebuf cpu_drain_writebuf + +/* + * Macros for manipulating CPU interrupts + */ +static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); + +static __inline u_int32_t +__set_cpsr_c(u_int bic, u_int eor) +{ + u_int32_t tmp, ret; + + __asm __volatile( + "mrs %0, cpsr\n" /* Get the CPSR */ + "bic %1, %0, %2\n" /* Clear bits */ + "eor %1, %1, %3\n" /* XOR bits */ + "msr cpsr_c, %1\n" /* Set the control field of CPSR */ + : "=&r" (ret), "=&r" (tmp) + : "r" (bic), "r" (eor) : "memory"); + + return ret; +} + +#define disable_interrupts(mask) \ + (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ + (mask) & (I32_bit | F32_bit))) + +#define enable_interrupts(mask) \ + (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) + +#define restore_interrupts(old_cpsr) \ + (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) + +#define intr_disable() \ + disable_interrupts(I32_bit | F32_bit) +#define intr_restore(s) \ + restore_interrupts(s) +/* Functions to manipulate the CPSR. */ +u_int SetCPSR(u_int bic, u_int eor); +u_int GetCPSR(void); + +/* + * Functions to manipulate cpu r13 + * (in arm/arm32/setstack.S) + */ + +void set_stackptr (u_int mode, u_int address); +u_int get_stackptr (u_int mode); + +/* + * Miscellany + */ + +int get_pc_str_offset (void); + +/* + * CPU functions from locore.S + */ + +void cpu_reset (void) __attribute__((__noreturn__)); + +/* + * Cache info variables. + */ + +/* PRIMARY CACHE VARIABLES */ +extern int arm_picache_size; +extern int arm_picache_line_size; +extern int arm_picache_ways; + +extern int arm_pdcache_size; /* and unified */ +extern int arm_pdcache_line_size; +extern int arm_pdcache_ways; + +extern int arm_pcache_type; +extern int arm_pcache_unified; + +extern int arm_dcache_align; +extern int arm_dcache_align_mask; + +#endif /* _KERNEL */ +#endif /* _MACHINE_CPUFUNC_HH_ */ + +/* End of cpufunc.h */ diff --git a/freebsd/sys/arm/include/machine/in_cksum.h b/freebsd/sys/arm/include/machine/in_cksum.h new file mode 100644 index 00000000..5e3e9333 --- /dev/null +++ b/freebsd/sys/arm/include/machine/in_cksum.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from tahoe: in_cksum.c 1.2 86/01/05 + * from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91 + * from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp + * $FreeBSD$ + */ + +#ifndef _MACHINE_IN_CKSUM_HH_ +#define _MACHINE_IN_CKSUM_HH_ 1 + +#include + +#ifdef _KERNEL +u_short in_cksum(struct mbuf *m, int len); +u_short in_addword(u_short sum, u_short b); +u_short in_cksum_skip(struct mbuf *m, int len, int skip); +u_int do_cksum(const void *, int); +u_int in_cksum_hdr(const struct ip *); + +static __inline u_short +in_pseudo(u_int sum, u_int b, u_int c) +{ + __asm __volatile("adds %0, %0, %1\n" + "adcs %0, %0, %2\n" + "adc %0, %0, #0\n" + : "+r" (sum) + : "r" (b), "r" (c)); + sum = (sum & 0xffff) + (sum >> 16); + if (sum > 0xffff) + sum -= 0xffff; + return (sum); +} + +#endif /* _KERNEL */ +#endif /* _MACHINE_IN_CKSUM_HH_ */ diff --git a/freebsd/sys/arm/include/machine/legacyvar.h b/freebsd/sys/arm/include/machine/legacyvar.h new file mode 100644 index 00000000..4771faf5 --- /dev/null +++ b/freebsd/sys/arm/include/machine/legacyvar.h @@ -0,0 +1,57 @@ +/*- + * Copyright (c) 2000 Peter Wemm + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_LEGACYVAR_HH_ +#define _MACHINE_LEGACYVAR_HH_ + +enum legacy_device_ivars { + LEGACY_IVAR_PCIDOMAIN, + LEGACY_IVAR_PCIBUS +}; + +#define LEGACY_ACCESSOR(var, ivar, type) \ + __BUS_ACCESSOR(legacy, var, LEGACY, ivar, type) + +LEGACY_ACCESSOR(pcidomain, PCIDOMAIN, uint32_t) +LEGACY_ACCESSOR(pcibus, PCIBUS, uint32_t) + +#undef LEGACY_ACCESSOR + +int legacy_pcib_maxslots(device_t dev); +uint32_t legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, + u_int reg, int bytes); +int legacy_pcib_read_ivar(device_t dev, device_t child, int which, + uintptr_t *result); +void legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, + u_int reg, u_int32_t data, int bytes); +int legacy_pcib_write_ivar(device_t dev, device_t child, int which, + uintptr_t value); +struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child, + int type, int *rid, u_long start, u_long end, u_long count, u_int flags); + +#endif /* !_MACHINE_LEGACYVAR_HH_ */ diff --git a/freebsd/sys/arm/include/machine/pci_cfgreg.h b/freebsd/sys/arm/include/machine/pci_cfgreg.h new file mode 100644 index 00000000..bc72418d --- /dev/null +++ b/freebsd/sys/arm/include/machine/pci_cfgreg.h @@ -0,0 +1,52 @@ +/*- + * Copyright (c) 1997, Stefan Esser + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#define CONF1_ADDR_PORT 0x0cf8 +#define CONF1_DATA_PORT 0x0cfc + +#define CONF1_ENABLE 0x80000000ul +#define CONF1_ENABLE_CHK 0x80000000ul +#define CONF1_ENABLE_MSK 0x7f000000ul +#define CONF1_ENABLE_CHK1 0xff000001ul +#define CONF1_ENABLE_MSK1 0x80000001ul +#define CONF1_ENABLE_RES1 0x80000000ul + +#define CONF2_ENABLE_PORT 0x0cf8 +#define CONF2_FORWARD_PORT 0x0cfa + +#define CONF2_ENABLE_CHK 0x0e +#define CONF2_ENABLE_RES 0x0e + +int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus); +int pci_cfgregopen(void); +u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes); +void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes); +void pci_pir_open(void); +int pci_pir_probe(int bus, int require_parse); +int pci_pir_route_interrupt(int bus, int device, int func, int pin); diff --git a/freebsd/sys/arm/pci/pci_bus.c b/freebsd/sys/arm/pci/pci_bus.c new file mode 100644 index 00000000..ec62ec14 --- /dev/null +++ b/freebsd/sys/arm/pci/pci_bus.c @@ -0,0 +1,729 @@ +#include + +/*- + * Copyright (c) 1997, Stefan Esser + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#ifdef CPU_ELAN +#include +#endif +#include +#include +#include + +#include + +#ifndef __rtems__ +static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev, + int pin); +#else /* __rtems__ */ +int pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin); +#endif /* __rtems__ */ + + +int +legacy_pcib_maxslots(device_t dev) +{ + return 31; +} + +/* read configuration space register */ + +#ifdef __rtems__ +uint32_t +legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, + u_int reg, int bytes) +#else +u_int32_t +legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, + u_int reg, int bytes) +#endif +{ + return(pci_cfgregread(bus, slot, func, reg, bytes)); +} + +/* write configuration space register */ + +void +legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, + u_int reg, u_int32_t data, int bytes) +{ + pci_cfgregwrite(bus, slot, func, reg, data, bytes); +} + +/* Pass MSI requests up to the nexus. */ + +static int +legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, + int *irqs) +{ + device_t bus; + + bus = device_get_parent(pcib); + return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, + irqs)); +} + +static int +legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) +{ + device_t bus; + + bus = device_get_parent(pcib); + return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); +} + +static int +legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, + uint32_t *data) +{ + device_t bus; + + bus = device_get_parent(pcib); + return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data)); +} + +static const char * +legacy_pcib_is_host_bridge(int bus, int slot, int func, + uint32_t id, uint8_t class, uint8_t subclass, + uint8_t *busnum) +{ + const char *s = NULL; + static uint8_t pxb[4]; /* hack for 450nx */ + + *busnum = 0; + + switch (id) { + case 0x12258086: + s = "Intel 824?? host to PCI bridge"; + /* XXX This is a guess */ + /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */ + *busnum = bus; + break; + case 0x71208086: + s = "Intel 82810 (i810 GMCH) Host To Hub bridge"; + break; + case 0x71228086: + s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge"; + break; + case 0x71248086: + s = "Intel 82810E (i810E GMCH) Host To Hub bridge"; + break; + case 0x11308086: + s = "Intel 82815 (i815 GMCH) Host To Hub bridge"; + break; + case 0x71808086: + s = "Intel 82443LX (440 LX) host to PCI bridge"; + break; + case 0x71908086: + s = "Intel 82443BX (440 BX) host to PCI bridge"; + break; + case 0x71928086: + s = "Intel 82443BX host to PCI bridge (AGP disabled)"; + break; + case 0x71948086: + s = "Intel 82443MX host to PCI bridge"; + break; + case 0x71a08086: + s = "Intel 82443GX host to PCI bridge"; + break; + case 0x71a18086: + s = "Intel 82443GX host to AGP bridge"; + break; + case 0x71a28086: + s = "Intel 82443GX host to PCI bridge (AGP disabled)"; + break; + case 0x84c48086: + s = "Intel 82454KX/GX (Orion) host to PCI bridge"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1); + break; + case 0x84ca8086: + /* + * For the 450nx chipset, there is a whole bundle of + * things pretending to be host bridges. The MIOC will + * be seen first and isn't really a pci bridge (the + * actual busses are attached to the PXB's). We need to + * read the registers of the MIOC to figure out the + * bus numbers for the PXB channels. + * + * Since the MIOC doesn't have a pci bus attached, we + * pretend it wasn't there. + */ + pxb[0] = legacy_pcib_read_config(0, bus, slot, func, + 0xd0, 1); /* BUSNO[0] */ + pxb[1] = legacy_pcib_read_config(0, bus, slot, func, + 0xd1, 1) + 1; /* SUBA[0]+1 */ + pxb[2] = legacy_pcib_read_config(0, bus, slot, func, + 0xd3, 1); /* BUSNO[1] */ + pxb[3] = legacy_pcib_read_config(0, bus, slot, func, + 0xd4, 1) + 1; /* SUBA[1]+1 */ + return NULL; + case 0x84cb8086: + switch (slot) { + case 0x12: + s = "Intel 82454NX PXB#0, Bus#A"; + *busnum = pxb[0]; + break; + case 0x13: + s = "Intel 82454NX PXB#0, Bus#B"; + *busnum = pxb[1]; + break; + case 0x14: + s = "Intel 82454NX PXB#1, Bus#A"; + *busnum = pxb[2]; + break; + case 0x15: + s = "Intel 82454NX PXB#1, Bus#B"; + *busnum = pxb[3]; + break; + } + break; + case 0x1A308086: + s = "Intel 82845 Host to PCI bridge"; + break; + + /* AMD -- vendor 0x1022 */ + case 0x30001022: + s = "AMD Elan SC520 host to PCI bridge"; +#ifdef CPU_ELAN + init_AMD_Elan_sc520(); +#else + printf( +"*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n"); +#endif + break; + case 0x70061022: + s = "AMD-751 host to PCI bridge"; + break; + case 0x700e1022: + s = "AMD-761 host to PCI bridge"; + break; + + /* SiS -- vendor 0x1039 */ + case 0x04961039: + s = "SiS 85c496"; + break; + case 0x04061039: + s = "SiS 85c501"; + break; + case 0x06011039: + s = "SiS 85c601"; + break; + case 0x55911039: + s = "SiS 5591 host to PCI bridge"; + break; + case 0x00011039: + s = "SiS 5591 host to AGP bridge"; + break; + + /* VLSI -- vendor 0x1004 */ + case 0x00051004: + s = "VLSI 82C592 Host to PCI bridge"; + break; + + /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */ + /* totally. Please let me know if anything wrong. -F */ + /* XXX need info on the MVP3 -- any takers? */ + case 0x05981106: + s = "VIA 82C598MVP (Apollo MVP3) host bridge"; + break; + + /* AcerLabs -- vendor 0x10b9 */ + /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ + /* id is '10b9" but the register always shows "10b9". -Foxfair */ + case 0x154110b9: + s = "AcerLabs M1541 (Aladdin-V) PCI host bridge"; + break; + + /* OPTi -- vendor 0x1045 */ + case 0xc7011045: + s = "OPTi 82C700 host to PCI bridge"; + break; + case 0xc8221045: + s = "OPTi 82C822 host to PCI Bridge"; + break; + + /* ServerWorks -- vendor 0x1166 */ + case 0x00051166: + s = "ServerWorks NB6536 2.0HE host to PCI bridge"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); + break; + + case 0x00061166: + /* FALLTHROUGH */ + case 0x00081166: + /* FALLTHROUGH */ + case 0x02011166: + /* FALLTHROUGH */ + case 0x010f1014: /* IBM re-badged ServerWorks chipset */ + s = "ServerWorks host to PCI bridge"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); + break; + + case 0x00091166: + s = "ServerWorks NB6635 3.0LE host to PCI bridge"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); + break; + + case 0x00101166: + s = "ServerWorks CIOB30 host to PCI bridge"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); + break; + + case 0x00111166: + /* FALLTHROUGH */ + case 0x03021014: /* IBM re-badged ServerWorks chipset */ + s = "ServerWorks CMIC-HE host to PCI-X bridge"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); + break; + + /* XXX unknown chipset, but working */ + case 0x00171166: + /* FALLTHROUGH */ + case 0x01011166: + case 0x01101166: + case 0x02251166: + s = "ServerWorks host to PCI bridge(unknown chipset)"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); + break; + + /* Compaq/HP -- vendor 0x0e11 */ + case 0x60100e11: + s = "Compaq/HP Model 6010 HotPlug PCI Bridge"; + *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1); + break; + + /* Integrated Micro Solutions -- vendor 0x10e0 */ + case 0x884910e0: + s = "Integrated Micro Solutions VL Bridge"; + break; + + default: + if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) + s = "Host to PCI bridge"; + break; + } + + return s; +} + +/* + * Scan the first pci bus for host-pci bridges and add pcib instances + * to the nexus for each bridge. + */ +static void +legacy_pcib_identify(driver_t *driver, device_t parent) +{ + int bus, slot, func; + u_int8_t hdrtype; + int found = 0; + int pcifunchigh; + int found824xx = 0; + int found_orion = 0; + device_t child; + devclass_t pci_devclass; + + if (pci_cfgregopen() == 0) + return; + /* + * Check to see if we haven't already had a PCI bus added + * via some other means. If we have, bail since otherwise + * we're going to end up duplicating it. + */ + if ((pci_devclass = devclass_find("pci")) && + devclass_get_device(pci_devclass, 0)) + return; + + + bus = 0; + retry: + for (slot = 0; slot <= PCI_SLOTMAX; slot++) { + func = 0; + hdrtype = legacy_pcib_read_config(0, bus, slot, func, + PCIR_HDRTYPE, 1); + /* + * When enumerating bus devices, the standard says that + * one should check the header type and ignore the slots whose + * header types that the software doesn't know about. We use + * this to filter out devices. + */ + if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) + continue; + if ((hdrtype & PCIM_MFDEV) && + (!found_orion || hdrtype != 0xff)) + pcifunchigh = PCI_FUNCMAX; + else + pcifunchigh = 0; + for (func = 0; func <= pcifunchigh; func++) { + /* + * Read the IDs and class from the device. + */ + u_int32_t id; + u_int8_t class, subclass, busnum; + const char *s; + device_t *devs; + int ndevs, i; + + id = legacy_pcib_read_config(0, bus, slot, func, + PCIR_DEVVENDOR, 4); + if (id == -1) + continue; + class = legacy_pcib_read_config(0, bus, slot, func, + PCIR_CLASS, 1); + subclass = legacy_pcib_read_config(0, bus, slot, func, + PCIR_SUBCLASS, 1); + + s = legacy_pcib_is_host_bridge(bus, slot, func, + id, class, subclass, + &busnum); + if (s == NULL) + continue; + + /* + * Check to see if the physical bus has already + * been seen. Eg: hybrid 32 and 64 bit host + * bridges to the same logical bus. + */ + if (device_get_children(parent, &devs, &ndevs) == 0) { + for (i = 0; s != NULL && i < ndevs; i++) { + if (strcmp(device_get_name(devs[i]), + "pcib") != 0) + continue; + if (legacy_get_pcibus(devs[i]) == busnum) + s = NULL; + } + free(devs, M_TEMP); + } + + if (s == NULL) + continue; + /* + * Add at priority 100 to make sure we + * go after any motherboard resources + */ + child = BUS_ADD_CHILD(parent, 100, + "pcib", busnum); + device_set_desc(child, s); + legacy_set_pcibus(child, busnum); + + found = 1; + if (id == 0x12258086) + found824xx = 1; + if (id == 0x84c48086) + found_orion = 1; + } + } + if (found824xx && bus == 0) { + bus++; + goto retry; + } + + /* + * Make sure we add at least one bridge since some old + * hardware doesn't actually have a host-pci bridge device. + * Note that pci_cfgregopen() thinks we have PCI devices.. + */ + if (!found) { + if (bootverbose) + printf( + "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n"); + child = BUS_ADD_CHILD(parent, 100, "pcib", 0); + legacy_set_pcibus(child, 0); + } +} + +static int +legacy_pcib_probe(device_t dev) +{ + + if (pci_cfgregopen() == 0) + return ENXIO; + return -100; +} + +static int +legacy_pcib_attach(device_t dev) +{ + device_t pir; + int bus; + + /* + * Look for a PCI BIOS interrupt routing table as that will be + * our method of routing interrupts if we have one. + */ + bus = pcib_get_bus(dev); +#ifndef __rtems__ + if (pci_pir_probe(bus, 0)) { + pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0); + if (pir != NULL) + device_probe_and_attach(pir); + } +#else /* __rtems__ */ +#endif /* __rtems__ */ + device_add_child(dev, "pci", bus); + return bus_generic_attach(dev); +} + +int +legacy_pcib_read_ivar(device_t dev, device_t child, int which, + uintptr_t *result) +{ + + switch (which) { + case PCIB_IVAR_DOMAIN: + *result = 0; + return 0; + case PCIB_IVAR_BUS: + *result = legacy_get_pcibus(dev); + return 0; + } + return ENOENT; +} + +int +legacy_pcib_write_ivar(device_t dev, device_t child, int which, + uintptr_t value) +{ + + switch (which) { + case PCIB_IVAR_DOMAIN: + return EINVAL; + case PCIB_IVAR_BUS: + legacy_set_pcibus(dev, value); + return 0; + } + return ENOENT; +} + +SYSCTL_DECL(_hw_pci); + +static unsigned long legacy_host_mem_start = 0x80000000; +TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start); +SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, + &legacy_host_mem_start, 0x80000000, + "Limit the host bridge memory to being above this address. Must be\n\ +set at boot via a tunable."); + +struct resource * +legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, + u_long start, u_long end, u_long count, u_int flags) +{ + /* + * If no memory preference is given, use upper 32MB slot most + * bioses use for their memory window. Typically other bridges + * before us get in the way to assert their preferences on memory. + * Hardcoding like this sucks, so a more MD/MI way needs to be + * found to do it. This is typically only used on older laptops + * that don't have pci busses behind pci bridge, so assuming > 32MB + * is liekly OK. + * + * However, this can cause problems for other chipsets, so we make + * this tunable by hw.pci.host_mem_start. + */ + if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL) + start = legacy_host_mem_start; + if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL) + start = 0x1000; + return (bus_generic_alloc_resource(dev, child, type, rid, start, end, + count, flags)); +} + +static device_method_t legacy_pcib_methods[] = { + /* Device interface */ + DEVMETHOD(device_identify, legacy_pcib_identify), + DEVMETHOD(device_probe, legacy_pcib_probe), + DEVMETHOD(device_attach, legacy_pcib_attach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + + /* Bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar), + DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar), + DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource), + DEVMETHOD(bus_release_resource, bus_generic_release_resource), + DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), + DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), + DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), + DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), + + /* pcib interface */ + DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots), + DEVMETHOD(pcib_read_config, legacy_pcib_read_config), + DEVMETHOD(pcib_write_config, legacy_pcib_write_config), + DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt), + DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi), + DEVMETHOD(pcib_release_msi, pcib_release_msi), + DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix), + DEVMETHOD(pcib_release_msix, pcib_release_msix), + DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi), + + { 0, 0 } +}; + +static devclass_t hostb_devclass; + +DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1); +DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0); + + +#ifndef __rtems__ +/* + * Install placeholder to claim the resources owned by the + * PCI bus interface. This could be used to extract the + * config space registers in the extreme case where the PnP + * ID is available and the PCI BIOS isn't, but for now we just + * eat the PnP ID and do nothing else. + * + * XXX we should silence this probe, as it will generally confuse + * people. + */ +static struct isa_pnp_id pcibus_pnp_ids[] = { + { 0x030ad041 /* PNP0A03 */, "PCI Bus" }, + { 0x080ad041 /* PNP0A08 */, "PCIe Bus" }, + { 0 } +}; + +static int +pcibus_pnp_probe(device_t dev) +{ + int result; + + if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0) + device_quiet(dev); + return(result); +} + +static int +pcibus_pnp_attach(device_t dev) +{ + return(0); +} + +static device_method_t pcibus_pnp_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, pcibus_pnp_probe), + DEVMETHOD(device_attach, pcibus_pnp_attach), + DEVMETHOD(device_detach, bus_generic_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + { 0, 0 } +}; + +static devclass_t pcibus_pnp_devclass; + +DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1); +DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0); + + +/* + * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges + * that appear in the PCIBIOS Interrupt Routing Table to use the routing + * table for interrupt routing when possible. + */ +static int pcibios_pcib_probe(device_t bus); + +static device_method_t pcibios_pcib_pci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, pcibios_pcib_probe), + DEVMETHOD(device_attach, pcib_attach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + + /* Bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_read_ivar, pcib_read_ivar), + DEVMETHOD(bus_write_ivar, pcib_write_ivar), + DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), + DEVMETHOD(bus_release_resource, bus_generic_release_resource), + DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), + DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), + DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), + DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), + + /* pcib interface */ + DEVMETHOD(pcib_maxslots, pcib_maxslots), + DEVMETHOD(pcib_read_config, pcib_read_config), + DEVMETHOD(pcib_write_config, pcib_write_config), + DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt), + DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), + DEVMETHOD(pcib_release_msi, pcib_release_msi), + DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), + DEVMETHOD(pcib_release_msix, pcib_release_msix), + DEVMETHOD(pcib_map_msi, pcib_map_msi), + + {0, 0} +}; + +static devclass_t pcib_devclass; + +DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods, + sizeof(struct pcib_softc)); +DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0); + +static int +pcibios_pcib_probe(device_t dev) +{ + int bus; + + if ((pci_get_class(dev) != PCIC_BRIDGE) || + (pci_get_subclass(dev) != PCIS_BRIDGE_PCI)) + return (ENXIO); + bus = pci_read_config(dev, PCIR_SECBUS_1, 1); + if (bus == 0) + return (ENXIO); + if (!pci_pir_probe(bus, 1)) + return (ENXIO); + device_set_desc(dev, "PCIBIOS PCI-PCI bridge"); + return (-2000); +} + +static int +pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin) +{ + return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev), + pci_get_function(dev), pin)); +} +#endif /* __rtems__ */ -- cgit v1.2.3