nexus: Add ZynqMP SLCR driver

Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.

1 files changed, 1 insertions, 0 deletions

diff --git a/libbsd.py b/libbsd.py
index 28617d21..16e81565 100644
--- a/libbsd.py
+++ b/libbsd.py
@@ -1423,6 +1423,7 @@ class dev_net(builder.Module):
         self.addRTEMSKernelSourceFiles(
             [
                 'sys/dev/mii/ksz8091rnb_50MHz.c',
+                'sys/arm64/xilinx/zynqmp_slcr.c',
             ],
             mm.generator['source']()
         )