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author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-02-09 07:14:11 -0600 |
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committer | Joel Sherrill <joel@rtems.org> | 2021-03-10 08:57:59 -0600 |
commit | e256668d6e902dece2e18ae106303ba24085c07f (patch) | |
tree | ba2157acb23f9a07e32c0050b0532bd9b42122c6 /libbsd.py | |
parent | nexus: Switch ZynqMP platforms to CGEM3 (diff) | |
download | rtems-libbsd-e256668d6e902dece2e18ae106303ba24085c07f.tar.bz2 |
nexus: Add ZynqMP SLCR driver
Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
Diffstat (limited to '')
-rw-r--r-- | libbsd.py | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -1423,6 +1423,7 @@ class dev_net(builder.Module): self.addRTEMSKernelSourceFiles( [ 'sys/dev/mii/ksz8091rnb_50MHz.c', + 'sys/arm64/xilinx/zynqmp_slcr.c', ], mm.generator['source']() ) |