Update to FreeBSD 9.2

1 files changed, 206 insertions, 161 deletions

diff --git a/freebsd/sys/dev/pci/pci_pci.c b/freebsd/sys/dev/pci/pci_pci.c
index b0951024..bfaabf35 100644
--- a/freebsd/sys/dev/pci/pci_pci.c
+++ b/freebsd/sys/dev/pci/pci_pci.c
@@ -40,23 +40,24 @@ __FBSDID("$FreeBSD$");
 #include <rtems/bsd/sys/param.h>
 #include <sys/bus.h>
 #include <sys/kernel.h>
-#include <sys/libkern.h>
 #include <sys/malloc.h>
 #include <sys/module.h>
 #include <sys/rman.h>
 #include <sys/sysctl.h>
 #include <sys/systm.h>
 
-#include <machine/bus.h>
-#include <machine/resource.h>
-
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
+#include <dev/pci/pci_private.h>
 #include <dev/pci/pcib_private.h>
 
 #include <rtems/bsd/local/pcib_if.h>
 
 static int		pcib_probe(device_t dev);
+static int		pcib_suspend(device_t dev);
+static int		pcib_resume(device_t dev);
+static int		pcib_power_for_sleep(device_t pcib, device_t dev,
+			    int *pstate);
 
 static device_method_t pcib_methods[] = {
     /* Device interface */
@@ -64,8 +65,8 @@ static device_method_t pcib_methods[] = {
     DEVMETHOD(device_attach,		pcib_attach),
     DEVMETHOD(device_detach,		bus_generic_detach),
     DEVMETHOD(device_shutdown,		bus_generic_shutdown),
-    DEVMETHOD(device_suspend,		bus_generic_suspend),
-    DEVMETHOD(device_resume,		bus_generic_resume),
+    DEVMETHOD(device_suspend,		pcib_suspend),
+    DEVMETHOD(device_resume,		pcib_resume),
 
     /* Bus interface */
     DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
@@ -93,6 +94,7 @@ static device_method_t pcib_methods[] = {
     DEVMETHOD(pcib_alloc_msix,		pcib_alloc_msix),
     DEVMETHOD(pcib_release_msix,	pcib_release_msix),
     DEVMETHOD(pcib_map_msi,		pcib_map_msi),
+    DEVMETHOD(pcib_power_for_sleep,	pcib_power_for_sleep),
 
     DEVMETHOD_END
 };
@@ -100,7 +102,7 @@ static device_method_t pcib_methods[] = {
 static devclass_t pcib_devclass;
 
 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
-DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
+DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
 
 #ifdef NEW_PCIB
 /*
@@ -365,7 +367,161 @@ pcib_is_io_open(struct pcib_softc *sc)
 {
 	return (sc->iobase > 0 && sc->iobase < sc->iolimit);
 }
+
+/*
+ * Get current I/O decode.
+ */
+static void
+pcib_get_io_decode(struct pcib_softc *sc)
+{
+	device_t	dev;
+	uint32_t	iolow;
+
+	dev = sc->dev;
+
+	iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
+	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
+		sc->iobase = PCI_PPBIOBASE(
+		    pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
+	else
+		sc->iobase = PCI_PPBIOBASE(0, iolow);
+
+	iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
+	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
+		sc->iolimit = PCI_PPBIOLIMIT(
+		    pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
+	else
+		sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
+}
+
+/*
+ * Get current memory decode.
+ */
+static void
+pcib_get_mem_decode(struct pcib_softc *sc)
+{
+	device_t	dev;
+	pci_addr_t	pmemlow;
+
+	dev = sc->dev;
+
+	sc->membase = PCI_PPBMEMBASE(0,
+	    pci_read_config(dev, PCIR_MEMBASE_1, 2));
+	sc->memlimit = PCI_PPBMEMLIMIT(0,
+	    pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
+
+	pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
+	if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
+		sc->pmembase = PCI_PPBMEMBASE(
+		    pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
+	else
+		sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
+
+	pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
+	if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)	
+		sc->pmemlimit = PCI_PPBMEMLIMIT(
+		    pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
+	else
+		sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
+}
+
+/*
+ * Restore previous I/O decode.
+ */
+static void
+pcib_set_io_decode(struct pcib_softc *sc)
+{
+	device_t	dev;
+	uint32_t	iohi;
+
+	dev = sc->dev;
+
+	iohi = sc->iobase >> 16;
+	if (iohi > 0)
+		pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
+	pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
+
+	iohi = sc->iolimit >> 16;
+	if (iohi > 0)
+		pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
+	pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
+}
+
+/*
+ * Restore previous memory decode.
+ */
+static void
+pcib_set_mem_decode(struct pcib_softc *sc)
+{
+	device_t	dev;
+	pci_addr_t	pmemhi;
+
+	dev = sc->dev;
+
+	pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
+	pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
+
+	pmemhi = sc->pmembase >> 32;
+	if (pmemhi > 0)
+		pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
+	pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
+
+	pmemhi = sc->pmemlimit >> 32;
+	if (pmemhi > 0)
+		pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
+	pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
+}
+#endif
+
+/*
+ * Get current bridge configuration.
+ */
+static void
+pcib_cfg_save(struct pcib_softc *sc)
+{
+	device_t	dev;
+
+	dev = sc->dev;
+
+	sc->command = pci_read_config(dev, PCIR_COMMAND, 2);
+	sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1);
+	sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
+	sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
+	sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
+	sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
+#ifndef NEW_PCIB
+	if (sc->command & PCIM_CMD_PORTEN)
+		pcib_get_io_decode(sc);
+	if (sc->command & PCIM_CMD_MEMEN)
+		pcib_get_mem_decode(sc);
+#endif
+}
+
+/*
+ * Restore previous bridge configuration.
+ */
+static void
+pcib_cfg_restore(struct pcib_softc *sc)
+{
+	device_t	dev;
+
+	dev = sc->dev;
+
+	pci_write_config(dev, PCIR_COMMAND, sc->command, 2);
+	pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
+	pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1);
+	pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1);
+	pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2);
+	pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1);
+#ifdef NEW_PCIB
+	pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
+#else
+	if (sc->command & PCIM_CMD_PORTEN)
+		pcib_set_io_decode(sc);
+	if (sc->command & PCIM_CMD_MEMEN)
+		pcib_set_mem_decode(sc);
 #endif
+}
 
 /*
  * Generic device interface
@@ -385,9 +541,6 @@ void
 pcib_attach_common(device_t dev)
 {
     struct pcib_softc	*sc;
-#ifndef NEW_PCIB
-    uint8_t		iolow;
-#endif
     struct sysctl_ctx_list *sctx;
     struct sysctl_oid	*soid;
 
@@ -397,14 +550,9 @@ pcib_attach_common(device_t dev)
     /*
      * Get current bridge configuration.
      */
-    sc->command   = pci_read_config(dev, PCIR_COMMAND, 1);
-    sc->domain    = pci_get_domain(dev);
-    sc->pribus    = pci_read_config(dev, PCIR_PRIBUS_1, 1);
-    sc->secbus    = pci_read_config(dev, PCIR_SECBUS_1, 1);
-    sc->subbus    = pci_read_config(dev, PCIR_SUBBUS_1, 1);
-    sc->secstat   = pci_read_config(dev, PCIR_SECSTAT_1, 2);
-    sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
-    sc->seclat    = pci_read_config(dev, PCIR_SECLAT_1, 1);
+    sc->domain = pci_get_domain(dev);
+    sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
+    pcib_cfg_save(sc);
 
     /*
      * Setup sysctl reporting nodes
@@ -420,53 +568,6 @@ pcib_attach_common(device_t dev)
     SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
       CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number");
 
-#ifndef NEW_PCIB
-    /*
-     * Determine current I/O decode.
-     */
-    if (sc->command & PCIM_CMD_PORTEN) {
-	iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
-	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
-	    sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
-				       pci_read_config(dev, PCIR_IOBASEL_1, 1));
-	} else {
-	    sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
-	}
-
-	iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
-	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
-	    sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
-					 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
-	} else {
-	    sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
-	}
-    }
-
-    /*
-     * Determine current memory decode.
-     */
-    if (sc->command & PCIM_CMD_MEMEN) {
-	sc->membase   = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
-	sc->memlimit  = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
-	iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1);
-	if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
-	    sc->pmembase = PCI_PPBMEMBASE(
-		pci_read_config(dev, PCIR_PMBASEH_1, 4),
-		pci_read_config(dev, PCIR_PMBASEL_1, 2));
-	else
-	    sc->pmembase = PCI_PPBMEMBASE(0,
-		pci_read_config(dev, PCIR_PMBASEL_1, 2));
-	iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1);
-	if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)	
-	    sc->pmemlimit = PCI_PPBMEMLIMIT(
-		pci_read_config(dev, PCIR_PMLIMITH_1, 4),
-		pci_read_config(dev, PCIR_PMLIMITL_1, 2));
-	else
-	    sc->pmemlimit = PCI_PPBMEMLIMIT(0,
-		pci_read_config(dev, PCIR_PMLIMITL_1, 2));
-    }
-#endif
-
     /*
      * Quirk handling.
      */
@@ -527,6 +628,9 @@ pcib_attach_common(device_t dev)
     if (pci_msi_device_blacklisted(dev))
 	sc->flags |= PCIB_DISABLE_MSI;
 
+    if (pci_msix_device_blacklisted(dev))
+	sc->flags |= PCIB_DISABLE_MSIX;
+
     /*
      * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
      * but have a ProgIF of 0x80.  The 82801 family (AA, AB, BAM/CAM,
@@ -614,6 +718,37 @@ pcib_attach(device_t dev)
 }
 
 int
+pcib_suspend(device_t dev)
+{
+	device_t	pcib;
+	int		dstate, error;
+
+	pcib_cfg_save(device_get_softc(dev));
+	error = bus_generic_suspend(dev);
+	if (error == 0 && pci_do_power_suspend) {
+		dstate = PCI_POWERSTATE_D3;
+		pcib = device_get_parent(device_get_parent(dev));
+		if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
+			pci_set_powerstate(dev, dstate);
+	}
+	return (error);
+}
+
+int
+pcib_resume(device_t dev)
+{
+	device_t	pcib;
+
+	if (pci_do_power_resume) {
+		pcib = device_get_parent(device_get_parent(dev));
+		if (PCIB_POWER_FOR_SLEEP(pcib, dev, NULL) == 0)
+			pci_set_powerstate(dev, PCI_POWERSTATE_D0);
+	}
+	pcib_cfg_restore(device_get_softc(dev));
+	return (bus_generic_resume(dev));
+}
+
+int
 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 {
     struct pcib_softc	*sc = device_get_softc(dev);
@@ -645,18 +780,6 @@ pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 }
 
 #ifdef NEW_PCIB
-static const char *
-pcib_child_name(device_t child)
-{
-	static char buf[64];
-
-	if (device_get_nameunit(child) != NULL)
-		return (device_get_nameunit(child));
-	snprintf(buf, sizeof(buf), "pci%d:%d:%d:%d", pci_get_domain(child),
-	    pci_get_bus(child), pci_get_slot(child), pci_get_function(child));
-	return (buf);
-}
-
 /*
  * Attempt to allocate a resource from the existing resources assigned
  * to a window.
@@ -1263,7 +1386,7 @@ pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
 	struct pcib_softc *sc = device_get_softc(pcib);
 	device_t bus;
 
-	if (sc->flags & PCIB_DISABLE_MSI)
+	if (sc->flags & PCIB_DISABLE_MSIX)
 		return (ENXIO);
 	bus = device_get_parent(pcib);
 	return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
@@ -1296,90 +1419,12 @@ pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
 	return (0);
 }
 
-/*
- * Try to read the bus number of a host-PCI bridge using appropriate config
- * registers.
- */
+/* Pass request for device power state up to parent bridge. */
 int
-host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
-    uint8_t *busnum)
+pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
 {
-	uint32_t id;
-
-	id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
-	if (id == 0xffffffff)
-		return (0);
-
-	switch (id) {
-	case 0x12258086:
-		/* Intel 824?? */
-		/* XXX This is a guess */
-		/* *busnum = read_config(bus, slot, func, 0x41, 1); */
-		*busnum = bus;
-		break;
-	case 0x84c48086:
-		/* Intel 82454KX/GX (Orion) */
-		*busnum = read_config(bus, slot, func, 0x4a, 1);
-		break;
-	case 0x84ca8086:
-		/*
-		 * For the 450nx chipset, there is a whole bundle of
-		 * things pretending to be host bridges. The MIOC will 
-		 * be seen first and isn't really a pci bridge (the
-		 * actual busses are attached to the PXB's). We need to 
-		 * read the registers of the MIOC to figure out the
-		 * bus numbers for the PXB channels.
-		 *
-		 * Since the MIOC doesn't have a pci bus attached, we
-		 * pretend it wasn't there.
-		 */
-		return (0);
-	case 0x84cb8086:
-		switch (slot) {
-		case 0x12:
-			/* Intel 82454NX PXB#0, Bus#A */
-			*busnum = read_config(bus, 0x10, func, 0xd0, 1);
-			break;
-		case 0x13:
-			/* Intel 82454NX PXB#0, Bus#B */
-			*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
-			break;
-		case 0x14:
-			/* Intel 82454NX PXB#1, Bus#A */
-			*busnum = read_config(bus, 0x10, func, 0xd3, 1);
-			break;
-		case 0x15:
-			/* Intel 82454NX PXB#1, Bus#B */
-			*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
-			break;
-		}
-		break;
-
-		/* ServerWorks -- vendor 0x1166 */
-	case 0x00051166:
-	case 0x00061166:
-	case 0x00081166:
-	case 0x00091166:
-	case 0x00101166:
-	case 0x00111166:
-	case 0x00171166:
-	case 0x01011166:
-	case 0x010f1014:
-	case 0x01101166:
-	case 0x02011166:
-	case 0x02251166:
-	case 0x03021014:
-		*busnum = read_config(bus, slot, func, 0x44, 1);
-		break;
-
-		/* Compaq/HP -- vendor 0x0e11 */
-	case 0x60100e11:
-		*busnum = read_config(bus, slot, func, 0xc8, 1);
-		break;
-	default:
-		/* Don't know how to read bus number. */
-		return 0;
-	}
+	device_t bus;
 
-	return 1;
+	bus = device_get_parent(pcib);
+	return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
 }