Update to FreeBSD head 2016-08-23

Git mirror commit 9fe7c416e6abb28b1398fd3e5687099846800cfd.

4 files changed, 471 insertions, 270 deletions

diff --git a/freebsd/sys/arm/include/machine/cpufunc.h b/freebsd/sys/arm/include/machine/cpufunc.h
index 8ec1574f..911fc14c 100644
--- a/freebsd/sys/arm/include/machine/cpufunc.h
+++ b/freebsd/sys/arm/include/machine/cpufunc.h
@@ -48,8 +48,8 @@
 #ifndef __rtems__
 
 #include <sys/types.h>
+#include <machine/armreg.h>
 #include <machine/cpuconf.h>
-#include <machine/katelib.h> /* For in[bwl] and out[bwl] */
 
 static __inline void
 breakpoint(void)
@@ -60,33 +60,26 @@ breakpoint(void)
 struct cpu_functions {
 
 	/* CPU functions */
-	
-	u_int	(*cf_id)		(void);
+
 	void	(*cf_cpwait)		(void);
 
 	/* MMU functions */
 
 	u_int	(*cf_control)		(u_int bic, u_int eor);
-	void	(*cf_domains)		(u_int domains);
 	void	(*cf_setttb)		(u_int ttb);
-	u_int	(*cf_faultstatus)	(void);
-	u_int	(*cf_faultaddress)	(void);
 
 	/* TLB functions */
 
-	void	(*cf_tlb_flushID)	(void);	
-	void	(*cf_tlb_flushID_SE)	(u_int va);	
-	void	(*cf_tlb_flushI)	(void);
-	void	(*cf_tlb_flushI_SE)	(u_int va);	
+	void	(*cf_tlb_flushID)	(void);
+	void	(*cf_tlb_flushID_SE)	(u_int va);
 	void	(*cf_tlb_flushD)	(void);
-	void	(*cf_tlb_flushD_SE)	(u_int va);	
+	void	(*cf_tlb_flushD_SE)	(u_int va);
 
 	/*
 	 * Cache operations:
 	 *
 	 * We define the following primitives:
 	 *
-	 *	icache_sync_all		Synchronize I-cache
 	 *	icache_sync_range	Synchronize I-cache range
 	 *
 	 *	dcache_wbinv_all	Write-back and Invalidate D-cache
@@ -105,7 +98,13 @@ struct cpu_functions {
 	 *
 	 * There are some rules that must be followed:
 	 *
-	 *	I-cache Synch (all or range):
+	 *	ID-cache Invalidate All:
+	 *		Unlike other functions, this one must never write back.
+	 *		It is used to intialize the MMU when it is in an unknown
+	 *		state (such as when it may have lines tagged as valid
+	 *		that belong to a previous set of mappings).
+	 *
+	 *	I-cache Sync range:
 	 *		The goal is to synchronize the instruction stream,
 	 *		so you may beed to write-back dirty D-cache blocks
 	 *		first.  If a range is requested, and you can't
@@ -131,7 +130,6 @@ struct cpu_functions {
 	 *		Valid virtual addresses must be passed to each
 	 *		cache operation.
 	 */
-	void	(*cf_icache_sync_all)	(void);
 	void	(*cf_icache_sync_range)	(vm_offset_t, vm_size_t);
 
 	void	(*cf_dcache_wbinv_all)	(void);
@@ -139,52 +137,44 @@ struct cpu_functions {
 	void	(*cf_dcache_inv_range)	(vm_offset_t, vm_size_t);
 	void	(*cf_dcache_wb_range)	(vm_offset_t, vm_size_t);
 
+	void	(*cf_idcache_inv_all)	(void);
 	void	(*cf_idcache_wbinv_all)	(void);
 	void	(*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
 	void	(*cf_l2cache_wbinv_all) (void);
 	void	(*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
 	void	(*cf_l2cache_inv_range)	  (vm_offset_t, vm_size_t);
 	void	(*cf_l2cache_wb_range)	  (vm_offset_t, vm_size_t);
+	void	(*cf_l2cache_drain_writebuf)	  (void);
 
 	/* Other functions */
 
-	void	(*cf_flush_prefetchbuf)	(void);
 	void	(*cf_drain_writebuf)	(void);
-	void	(*cf_flush_brnchtgt_C)	(void);
-	void	(*cf_flush_brnchtgt_E)	(u_int va);
 
 	void	(*cf_sleep)		(int mode);
 
 	/* Soft functions */
 
-	int	(*cf_dataabt_fixup)	(void *arg);
-	int	(*cf_prefetchabt_fixup)	(void *arg);
-
 	void	(*cf_context_switch)	(void);
 
-	void	(*cf_setup)		(char *string);
+	void	(*cf_setup)		(void);
 };
 
 extern struct cpu_functions cpufuncs;
 extern u_int cputype;
 
-#define cpu_id()		cpufuncs.cf_id()
+#if __ARM_ARCH < 6
 #define	cpu_cpwait()		cpufuncs.cf_cpwait()
+#endif
 
 #define cpu_control(c, e)	cpufuncs.cf_control(c, e)
-#define cpu_domains(d)		cpufuncs.cf_domains(d)
+#if __ARM_ARCH < 6
 #define cpu_setttb(t)		cpufuncs.cf_setttb(t)
-#define cpu_faultstatus()	cpufuncs.cf_faultstatus()
-#define cpu_faultaddress()	cpufuncs.cf_faultaddress()
 
 #define	cpu_tlb_flushID()	cpufuncs.cf_tlb_flushID()
 #define	cpu_tlb_flushID_SE(e)	cpufuncs.cf_tlb_flushID_SE(e)
-#define	cpu_tlb_flushI()	cpufuncs.cf_tlb_flushI()
-#define	cpu_tlb_flushI_SE(e)	cpufuncs.cf_tlb_flushI_SE(e)
 #define	cpu_tlb_flushD()	cpufuncs.cf_tlb_flushD()
 #define	cpu_tlb_flushD_SE(e)	cpufuncs.cf_tlb_flushD_SE(e)
 
-#define	cpu_icache_sync_all()	cpufuncs.cf_icache_sync_all()
 #define	cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
 
 #define	cpu_dcache_wbinv_all()	cpufuncs.cf_dcache_wbinv_all()
@@ -192,110 +182,43 @@ extern u_int cputype;
 #define	cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
 #define	cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
 
+#define	cpu_idcache_inv_all()	cpufuncs.cf_idcache_inv_all()
 #define	cpu_idcache_wbinv_all()	cpufuncs.cf_idcache_wbinv_all()
 #define	cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
+#endif
 #define cpu_l2cache_wbinv_all()	cpufuncs.cf_l2cache_wbinv_all()
 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
+#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
 
-#define	cpu_flush_prefetchbuf()	cpufuncs.cf_flush_prefetchbuf()
+#if __ARM_ARCH < 6
 #define	cpu_drain_writebuf()	cpufuncs.cf_drain_writebuf()
-#define	cpu_flush_brnchtgt_C()	cpufuncs.cf_flush_brnchtgt_C()
-#define	cpu_flush_brnchtgt_E(e)	cpufuncs.cf_flush_brnchtgt_E(e)
-
+#endif
 #define cpu_sleep(m)		cpufuncs.cf_sleep(m)
 
-#define cpu_dataabt_fixup(a)		cpufuncs.cf_dataabt_fixup(a)
-#define cpu_prefetchabt_fixup(a)	cpufuncs.cf_prefetchabt_fixup(a)
-#define ABORT_FIXUP_OK		0	/* fixup succeeded */
-#define ABORT_FIXUP_FAILED	1	/* fixup failed */
-#define ABORT_FIXUP_RETURN	2	/* abort handler should return */
-
-#define cpu_setup(a)			cpufuncs.cf_setup(a)
+#define cpu_setup()			cpufuncs.cf_setup()
 
 int	set_cpufuncs		(void);
 #define ARCHITECTURE_NOT_PRESENT	1	/* known but not configured */
 #define ARCHITECTURE_NOT_SUPPORTED	2	/* not known */
 
 void	cpufunc_nullop		(void);
-int	cpufunc_null_fixup	(void *);
-int	early_abort_fixup	(void *);
-int	late_abort_fixup	(void *);
-u_int	cpufunc_id		(void);
+u_int	cpu_ident		(void);
 u_int	cpufunc_control		(u_int clear, u_int bic);
-void	cpufunc_domains		(u_int domains);
-u_int	cpufunc_faultstatus	(void);
-u_int	cpufunc_faultaddress	(void);
-
-#ifdef CPU_ARM3
-u_int	arm3_control		(u_int clear, u_int bic);
-void	arm3_cache_flush	(void);
-#endif	/* CPU_ARM3 */
-
-#if defined(CPU_ARM6) || defined(CPU_ARM7)
-void	arm67_setttb		(u_int ttb);
-void	arm67_tlb_flush		(void);
-void	arm67_tlb_purge		(u_int va);
-void	arm67_cache_flush	(void);
-void	arm67_context_switch	(void);
-#endif	/* CPU_ARM6 || CPU_ARM7 */
-
-#ifdef CPU_ARM6
-void	arm6_setup		(char *string);
-#endif	/* CPU_ARM6 */
-
-#ifdef CPU_ARM7
-void	arm7_setup		(char *string);
-#endif	/* CPU_ARM7 */
-
-#ifdef CPU_ARM7TDMI
-int	arm7_dataabt_fixup	(void *arg);
-void	arm7tdmi_setup		(char *string);
-void	arm7tdmi_setttb		(u_int ttb);
-void	arm7tdmi_tlb_flushID	(void);
-void	arm7tdmi_tlb_flushID_SE	(u_int va);
-void	arm7tdmi_cache_flushID	(void);
-void	arm7tdmi_context_switch	(void);
-#endif /* CPU_ARM7TDMI */
-
-#ifdef CPU_ARM8
-void	arm8_setttb		(u_int ttb);
-void	arm8_tlb_flushID	(void);
-void	arm8_tlb_flushID_SE	(u_int va);
-void	arm8_cache_flushID	(void);
-void	arm8_cache_flushID_E	(u_int entry);
-void	arm8_cache_cleanID	(void);
-void	arm8_cache_cleanID_E	(u_int entry);
-void	arm8_cache_purgeID	(void);
-void	arm8_cache_purgeID_E	(u_int entry);
-
-void	arm8_cache_syncI	(void);
-void	arm8_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
-void	arm8_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
-void	arm8_cache_purgeID_rng	(vm_offset_t start, vm_size_t end);
-void	arm8_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
-void	arm8_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
-
-void	arm8_context_switch	(void);
-
-void	arm8_setup		(char *string);
-
-u_int	arm8_clock_config	(u_int, u_int);
-#endif
-
-
-#if defined(CPU_FA526) || defined(CPU_FA626TE)
-void	fa526_setup		(char *arg);
+void	cpu_domains		(u_int domains);
+u_int	cpu_faultstatus		(void);
+u_int	cpu_faultaddress	(void);
+u_int	cpu_get_control		(void);
+u_int	cpu_pfr			(int);
+
+#if defined(CPU_FA526)
+void	fa526_setup		(void);
 void	fa526_setttb		(u_int ttb);
 void	fa526_context_switch	(void);
 void	fa526_cpu_sleep		(int);
-void	fa526_tlb_flushI_SE	(u_int);
 void	fa526_tlb_flushID_SE	(u_int);
-void	fa526_flush_prefetchbuf	(void);
-void	fa526_flush_brnchtgt_E	(u_int);
 
-void	fa526_icache_sync_all	(void);
 void	fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
 void	fa526_dcache_wbinv_all	(void);
 void	fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
@@ -306,54 +229,13 @@ void	fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
 #endif
 
 
-#ifdef CPU_SA110
-void	sa110_setup		(char *string);
-void	sa110_context_switch	(void);
-#endif	/* CPU_SA110 */
-
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-void	sa11x0_drain_readbuf	(void);
-
-void	sa11x0_context_switch	(void);
-void	sa11x0_cpu_sleep	(int mode);
- 
-void	sa11x0_setup		(char *string);
-#endif
-
-#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
-void	sa1_setttb		(u_int ttb);
-
-void	sa1_tlb_flushID_SE	(u_int va);
-
-void	sa1_cache_flushID	(void);
-void	sa1_cache_flushI	(void);
-void	sa1_cache_flushD	(void);
-void	sa1_cache_flushD_SE	(u_int entry);
-
-void	sa1_cache_cleanID	(void);
-void	sa1_cache_cleanD	(void);
-void	sa1_cache_cleanD_E	(u_int entry);
-
-void	sa1_cache_purgeID	(void);
-void	sa1_cache_purgeID_E	(u_int entry);
-void	sa1_cache_purgeD	(void);
-void	sa1_cache_purgeD_E	(u_int entry);
-
-void	sa1_cache_syncI		(void);
-void	sa1_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
-void	sa1_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
-void	sa1_cache_purgeID_rng	(vm_offset_t start, vm_size_t end);
-void	sa1_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
-void	sa1_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
-
-#endif
-
-#ifdef CPU_ARM9
+#if defined(CPU_ARM9) || defined(CPU_ARM9E)
 void	arm9_setttb		(u_int);
-
 void	arm9_tlb_flushID_SE	(u_int va);
+void	arm9_context_switch	(void);
+#endif
 
-void	arm9_icache_sync_all	(void);
+#if defined(CPU_ARM9)
 void	arm9_icache_sync_range	(vm_offset_t, vm_size_t);
 
 void	arm9_dcache_wbinv_all	(void);
@@ -364,9 +246,7 @@ void	arm9_dcache_wb_range	(vm_offset_t, vm_size_t);
 void	arm9_idcache_wbinv_all	(void);
 void	arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
 
-void	arm9_context_switch	(void);
-
-void	arm9_setup		(char *string);
+void	arm9_setup		(void);
 
 extern unsigned arm9_dcache_sets_max;
 extern unsigned arm9_dcache_sets_inc;
@@ -374,31 +254,8 @@ extern unsigned arm9_dcache_index_max;
 extern unsigned arm9_dcache_index_inc;
 #endif
 
-#if defined(CPU_ARM9E) || defined(CPU_ARM10)
-void	arm10_setttb		(u_int);
-
-void	arm10_tlb_flushID_SE	(u_int);
-void	arm10_tlb_flushI_SE	(u_int);
-
-void	arm10_icache_sync_all	(void);
-void	arm10_icache_sync_range	(vm_offset_t, vm_size_t);
-
-void	arm10_dcache_wbinv_all	(void);
-void	arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
-void	arm10_dcache_inv_range	(vm_offset_t, vm_size_t);
-void	arm10_dcache_wb_range	(vm_offset_t, vm_size_t);
-
-void	arm10_idcache_wbinv_all	(void);
-void	arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
-
-void	arm10_context_switch	(void);
-
-void	arm10_setup		(char *string);
-
-extern unsigned arm10_dcache_sets_max;
-extern unsigned arm10_dcache_sets_inc;
-extern unsigned arm10_dcache_index_max;
-extern unsigned arm10_dcache_index_inc;
+#if defined(CPU_ARM9E)
+void	arm10_setup		(void);
 
 u_int	sheeva_control_ext 		(u_int, u_int);
 void	sheeva_cpu_sleep		(int);
@@ -414,27 +271,65 @@ void	sheeva_l2cache_wb_range		(vm_offset_t, vm_size_t);
 void	sheeva_l2cache_wbinv_all	(void);
 #endif
 
-#ifdef CPU_ARM11
-void	arm11_setttb		(u_int);
-
-void	arm11_tlb_flushID_SE	(u_int);
-void	arm11_tlb_flushI_SE	(u_int);
-
-void	arm11_context_switch	(void);
+#if defined(CPU_MV_PJ4B)
+void	armv6_idcache_wbinv_all		(void);
+#endif
+#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
+void	armv7_setttb			(u_int);
+void	armv7_tlb_flushID		(void);
+void	armv7_tlb_flushID_SE		(u_int);
+void	armv7_icache_sync_range		(vm_offset_t, vm_size_t);
+void	armv7_idcache_wbinv_range	(vm_offset_t, vm_size_t);
+void	armv7_idcache_inv_all		(void);
+void	armv7_dcache_wbinv_all		(void);
+void	armv7_idcache_wbinv_all		(void);
+void	armv7_dcache_wbinv_range	(vm_offset_t, vm_size_t);
+void	armv7_dcache_inv_range		(vm_offset_t, vm_size_t);
+void	armv7_dcache_wb_range		(vm_offset_t, vm_size_t);
+void	armv7_cpu_sleep			(int);
+void	armv7_setup			(void);
+void	armv7_context_switch		(void);
+void	armv7_drain_writebuf		(void);
+void	armv7_sev			(void);
+u_int	armv7_auxctrl			(u_int, u_int);
+
+void	armadaxp_idcache_wbinv_all	(void);
+
+void 	cortexa_setup			(void);
+#endif
+#if defined(CPU_MV_PJ4B)
+void	pj4b_config			(void);
+void	pj4bv7_setup			(void);
+#endif
 
-void	arm11_setup		(char *string);
+#if defined(CPU_ARM1176)
 void	arm11_tlb_flushID	(void);
-void	arm11_tlb_flushI	(void);
+void	arm11_tlb_flushID_SE	(u_int);
 void	arm11_tlb_flushD	(void);
 void	arm11_tlb_flushD_SE	(u_int va);
 
+void	arm11_context_switch	(void);
+
 void	arm11_drain_writebuf	(void);
+
+void	armv6_dcache_wbinv_range	(vm_offset_t, vm_size_t);
+void	armv6_dcache_inv_range		(vm_offset_t, vm_size_t);
+void	armv6_dcache_wb_range		(vm_offset_t, vm_size_t);
+
+void	armv6_idcache_inv_all		(void);
+
+void    arm11x6_setttb                  (u_int);
+void    arm11x6_idcache_wbinv_all       (void);
+void    arm11x6_dcache_wbinv_all        (void);
+void    arm11x6_icache_sync_range       (vm_offset_t, vm_size_t);
+void    arm11x6_idcache_wbinv_range     (vm_offset_t, vm_size_t);
+void    arm11x6_setup                   (void);
+void    arm11x6_sleep                   (int);  /* no ref. for errata */
 #endif
 
-#if defined(CPU_ARM9E) || defined (CPU_ARM10)
+#if defined(CPU_ARM9E)
 void	armv5_ec_setttb(u_int);
 
-void	armv5_ec_icache_sync_all(void);
 void	armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
 
 void	armv5_ec_dcache_wbinv_all(void);
@@ -446,50 +341,21 @@ void	armv5_ec_idcache_wbinv_all(void);
 void	armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
 #endif
 
-#if defined (CPU_ARM10) || defined (CPU_ARM11)
-void	armv5_setttb(u_int);
-
-void	armv5_icache_sync_all(void);
-void	armv5_icache_sync_range(vm_offset_t, vm_size_t);
-
-void	armv5_dcache_wbinv_all(void);
-void	armv5_dcache_wbinv_range(vm_offset_t, vm_size_t);
-void	armv5_dcache_inv_range(vm_offset_t, vm_size_t);
-void	armv5_dcache_wb_range(vm_offset_t, vm_size_t);
-
-void	armv5_idcache_wbinv_all(void);
-void	armv5_idcache_wbinv_range(vm_offset_t, vm_size_t);
-
-extern unsigned armv5_dcache_sets_max;
-extern unsigned armv5_dcache_sets_inc;
-extern unsigned armv5_dcache_index_max;
-extern unsigned armv5_dcache_index_inc;
-#endif
-
-#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) ||	\
-  defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||	\
-  defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
-  defined(CPU_FA526) || defined(CPU_FA626TE) ||				\
+#if defined(CPU_ARM9) || defined(CPU_ARM9E) ||				\
+  defined(CPU_FA526) ||							\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
-  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
-  
+  defined(CPU_XSCALE_81342)
+
 void	armv4_tlb_flushID	(void);
-void	armv4_tlb_flushI	(void);
 void	armv4_tlb_flushD	(void);
 void	armv4_tlb_flushD_SE	(u_int va);
 
 void	armv4_drain_writebuf	(void);
+void	armv4_idcache_inv_all	(void);
 #endif
 
-#if defined(CPU_IXP12X0)
-void	ixp12x0_drain_readbuf	(void);
-void	ixp12x0_context_switch	(void);
-void	ixp12x0_setup		(char *string);
-#endif
-
-#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||	\
-  defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
-  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
+#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
+  defined(CPU_XSCALE_81342)
 void	xscale_cpwait		(void);
 
 void	xscale_cpu_sleep	(int mode);
@@ -526,9 +392,8 @@ void	xscale_cache_flushD_rng	(vm_offset_t start, vm_size_t end);
 
 void	xscale_context_switch	(void);
 
-void	xscale_setup		(char *string);
-#endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 
-	   CPU_XSCALE_80219 */
+void	xscale_setup		(void);
+#endif	/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
 
 #ifdef	CPU_XSCALE_81342
 
@@ -555,48 +420,66 @@ void	xscalec3_context_switch	(void);
 
 #endif /* CPU_XSCALE_81342 */
 
-#define tlb_flush	cpu_tlb_flushID
-#define setttb		cpu_setttb
-#define drain_writebuf	cpu_drain_writebuf
-
 /*
  * Macros for manipulating CPU interrupts
  */
-static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
+#if __ARM_ARCH < 6
+#define	__ARM_INTR_BITS		(PSR_I | PSR_F)
+#else
+#define	__ARM_INTR_BITS		(PSR_I | PSR_F | PSR_A)
+#endif
 
-static __inline u_int32_t
-__set_cpsr_c(u_int bic, u_int eor)
+static __inline uint32_t
+__set_cpsr(uint32_t bic, uint32_t eor)
 {
-	u_int32_t	tmp, ret;
+	uint32_t	tmp, ret;
 
 	__asm __volatile(
-		"mrs     %0, cpsr\n"	/* Get the CPSR */
-		"bic	 %1, %0, %2\n"	/* Clear bits */
-		"eor	 %1, %1, %3\n"	/* XOR bits */
-		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
+		"mrs     %0, cpsr\n"		/* Get the CPSR */
+		"bic	 %1, %0, %2\n"		/* Clear bits */
+		"eor	 %1, %1, %3\n"		/* XOR bits */
+		"msr     cpsr_xc, %1\n"		/* Set the CPSR */
 	: "=&r" (ret), "=&r" (tmp)
 	: "r" (bic), "r" (eor) : "memory");
 
 	return ret;
 }
 
-#define disable_interrupts(mask)					\
-	(__set_cpsr_c((mask) & (I32_bit | F32_bit), \
-		      (mask) & (I32_bit | F32_bit)))
+static __inline uint32_t
+disable_interrupts(uint32_t mask)
+{
+
+	return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
+}
+
+static __inline uint32_t
+enable_interrupts(uint32_t mask)
+{
 
-#define enable_interrupts(mask)						\
-	(__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))
+	return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
+}
 
-#define restore_interrupts(old_cpsr)					\
-	(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
+static __inline uint32_t
+restore_interrupts(uint32_t old_cpsr)
+{
 
-#define intr_disable()	\
-    disable_interrupts(I32_bit | F32_bit)
-#define intr_restore(s)	\
-    restore_interrupts(s)
-/* Functions to manipulate the CPSR. */
-u_int	SetCPSR(u_int bic, u_int eor);
-u_int	GetCPSR(void);
+	return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
+}
+
+static __inline register_t
+intr_disable(void)
+{
+
+	return (disable_interrupts(PSR_I | PSR_F));
+}
+
+static __inline void
+intr_restore(register_t s)
+{
+
+	restore_interrupts(s);
+}
+#undef __ARM_INTR_BITS
 
 /*
  * Functions to manipulate cpu r13
@@ -629,7 +512,7 @@ extern int	arm_picache_ways;
 
 extern int	arm_pdcache_size;	/* and unified */
 extern int	arm_pdcache_line_size;
-extern int	arm_pdcache_ways; 
+extern int	arm_pdcache_ways;
 
 extern int	arm_pcache_type;
 extern int	arm_pcache_unified;
@@ -637,6 +520,10 @@ extern int	arm_pcache_unified;
 extern int	arm_dcache_align;
 extern int	arm_dcache_align_mask;
 
+extern u_int	arm_cache_level;
+extern u_int	arm_cache_loc;
+extern u_int	arm_cache_type[14];
+
 #endif /* __rtems__ */
 #endif	/* _KERNEL */
 #endif	/* _MACHINE_CPUFUNC_H_ */
diff --git a/freebsd/sys/arm/include/machine/in_cksum.h b/freebsd/sys/arm/include/machine/in_cksum.h
index 633efa1f..72edfba9 100644
--- a/freebsd/sys/arm/include/machine/in_cksum.h
+++ b/freebsd/sys/arm/include/machine/in_cksum.h
@@ -10,7 +10,7 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
+ * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
diff --git a/freebsd/sys/arm/xilinx/zy7_slcr.c b/freebsd/sys/arm/xilinx/zy7_slcr.c
index 79be30a7..7ce502f9 100644
--- a/freebsd/sys/arm/xilinx/zy7_slcr.c
+++ b/freebsd/sys/arm/xilinx/zy7_slcr.c
@@ -88,7 +88,6 @@ extern void (*zynq7_cpu_reset);
 
 #define ZYNQ_DEFAULT_PS_CLK_FREQUENCY	33333333	/* 33.3 Mhz */
 
-
 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
 
 static char zynq_bootmode[64];
@@ -135,7 +134,6 @@ zy7_slcr_lock(struct zy7_slcr_softc *sc)
 	WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
 }
 
-
 #ifndef __rtems__
 static void
 zy7_slcr_cpu_reset(void)
@@ -185,11 +183,12 @@ zy7_slcr_preload_pl(void)
 
 	ZSLCR_UNLOCK(sc);
 }
+#endif /* __rtems__ */
 
 /* After PL configuration, enable level shifters and deassert top-level
  * PL resets.  Called from zy7_devcfg.c.  Optionally, the level shifters
  * can be left disabled but that's rare of an FPGA application. That option
- * is controled by a sysctl in the devcfg driver.
+ * is controlled by a sysctl in the devcfg driver.
  */
 void
 zy7_slcr_postload_pl(int en_level_shifters)
@@ -216,7 +215,6 @@ zy7_slcr_postload_pl(int en_level_shifters)
 
 	ZSLCR_UNLOCK(sc);
 }
-#endif /* __rtems__ */
 
 /* Override cgem_set_refclk() in gigabit ethernet driver
  * (sys/dev/cadence/if_cgem.c).  This function is called to
@@ -266,6 +264,296 @@ cgem_set_ref_clk(int unit, int frequency)
 	return (0);
 }
 
+/* 
+ * PL clocks management function
+ */
+int 
+zy7_pl_fclk_set_source(int unit, int source)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+	uint32_t reg;
+
+	if (!sc)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+
+	/* Unlock SLCR registers. */
+	zy7_slcr_unlock(sc);
+
+	/* Modify FPGAx source. */
+	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
+	reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK);
+	reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);
+	WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
+
+	/* Lock SLCR registers. */
+	zy7_slcr_lock(sc);
+
+	ZSLCR_UNLOCK(sc);
+
+	return (0);
+}
+
+int 
+zy7_pl_fclk_get_source(int unit)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+	uint32_t reg;
+	int source;
+
+	if (!sc)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+
+	/* Modify GEM reference clock. */
+	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
+	source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >> 
+	    ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT;
+
+	/* ZY7_PL_FCLK_SRC_IO is actually b0x */
+	if ((source & 2) == 0)
+		source = ZY7_PL_FCLK_SRC_IO;
+
+	ZSLCR_UNLOCK(sc);
+
+	return (source);
+}
+
+int
+zy7_pl_fclk_set_freq(int unit, int frequency)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+	int div0, div1;
+	int base_frequency;
+	uint32_t reg;
+	int source;
+
+	if (!sc)
+		return (-1);
+
+	source = zy7_pl_fclk_get_source(unit);
+	switch (source) {
+		case ZY7_PL_FCLK_SRC_IO:
+			base_frequency = io_pll_frequency;
+			break;
+
+		case ZY7_PL_FCLK_SRC_ARM:
+			base_frequency = arm_pll_frequency;
+			break;
+
+		case ZY7_PL_FCLK_SRC_DDR:
+			base_frequency = ddr_pll_frequency;
+			break;
+
+		default:
+			return (-1);
+	}
+
+	/* Find suitable divisor pairs.  Round result to nearest khz
+	 * to test for match.
+	 */
+	for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
+		div0 = (base_frequency + div1 * frequency / 2) /
+			div1 / frequency;
+		if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX &&
+		    ((base_frequency / div0 / div1) + 500) / 1000 ==
+		    (frequency + 500) / 1000)
+			break;
+	}
+
+	if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+
+	/* Unlock SLCR registers. */
+	zy7_slcr_unlock(sc);
+
+	/* Modify FPGAx reference clock. */
+	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
+	reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK |
+	    ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK);
+	reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |
+	    (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT);
+	WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
+
+	/* Lock SLCR registers. */
+	zy7_slcr_lock(sc);
+
+	ZSLCR_UNLOCK(sc);
+
+	return (base_frequency / div0 / div1);
+}
+
+int
+zy7_pl_fclk_get_freq(int unit)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+	int div0, div1;
+	int base_frequency;
+	int frequency;
+	uint32_t reg;
+	int source;
+
+	if (!sc)
+		return (-1);
+
+	source = zy7_pl_fclk_get_source(unit);
+	switch (source) {
+		case ZY7_PL_FCLK_SRC_IO:
+			base_frequency = io_pll_frequency;
+			break;
+
+		case ZY7_PL_FCLK_SRC_ARM:
+			base_frequency = arm_pll_frequency;
+			break;
+
+		case ZY7_PL_FCLK_SRC_DDR:
+			base_frequency = ddr_pll_frequency;
+			break;
+
+		default:
+			return (-1);
+	}
+
+	ZSLCR_LOCK(sc);
+
+	/* Modify FPGAx reference clock. */
+	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
+	div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>
+	    ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT;
+	div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>
+	    ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT;
+
+	ZSLCR_UNLOCK(sc);
+
+	if (div0 == 0)
+		div0 = 1;
+
+	if (div1 == 0)
+		div1 = 1;
+
+	frequency = (base_frequency / div0 / div1);
+	/* Round to KHz */
+	frequency = (frequency + 500) / 1000;
+	frequency = frequency * 1000;
+
+	return (frequency);
+}
+
+int 
+zy7_pl_fclk_enable(int unit)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+
+	if (!sc)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+
+	/* Unlock SLCR registers. */
+	zy7_slcr_unlock(sc);
+
+	WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
+	WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0);
+
+	/* Lock SLCR registers. */
+	zy7_slcr_lock(sc);
+
+	ZSLCR_UNLOCK(sc);
+
+	return (0);
+}
+
+int 
+zy7_pl_fclk_disable(int unit)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+
+	if (!sc)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+
+	/* Unlock SLCR registers. */
+	zy7_slcr_unlock(sc);
+
+	WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
+	WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
+
+	/* Lock SLCR registers. */
+	zy7_slcr_lock(sc);
+
+	ZSLCR_UNLOCK(sc);
+
+	return (0);
+}
+
+int 
+zy7_pl_fclk_enabled(int unit)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+	uint32_t reg;
+
+	if (!sc)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+	reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
+	ZSLCR_UNLOCK(sc);
+
+	return !(reg & 1);
+}
+
+int
+zy7_pl_level_shifters_enabled()
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+
+	uint32_t reg;
+
+	if (!sc)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+	reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
+	ZSLCR_UNLOCK(sc);
+
+	return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL);
+}
+
+void
+zy7_pl_level_shifters_enable()
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+
+	if (!sc)
+		return;
+
+	ZSLCR_LOCK(sc);
+	zy7_slcr_unlock(sc);
+	WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
+	zy7_slcr_lock(sc);
+	ZSLCR_UNLOCK(sc);
+}
+
+void
+zy7_pl_level_shifters_disable()
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+
+	if (!sc)
+		return;
+
+	ZSLCR_LOCK(sc);
+	zy7_slcr_unlock(sc);
+	WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
+	zy7_slcr_lock(sc);
+	ZSLCR_UNLOCK(sc);
+}
+
 static int
 zy7_slcr_probe(device_t dev)
 {
diff --git a/freebsd/sys/arm/xilinx/zy7_slcr.h b/freebsd/sys/arm/xilinx/zy7_slcr.h
index 70c46619..3afec02a 100644
--- a/freebsd/sys/arm/xilinx/zy7_slcr.h
+++ b/freebsd/sys/arm/xilinx/zy7_slcr.h
@@ -37,7 +37,6 @@
  * are in appendix B.28.
  */
 
-
 #ifndef _ZY7_SLCR_H_
 #define _ZY7_SLCR_H_
 
@@ -148,10 +147,19 @@
 #define ZY7_SLCR_DBG_CLK_CTRL		0x0164
 #define ZY7_SLCR_PCAP_CLK_CTRL		0x0168
 #define ZY7_SLCR_TOPSW_CLK_CTRL		0x016c	/* central intercnn clk ctrl */
-#define ZY7_SLCR_FPGA0_CLK_CTRL		0x0170
-#define ZY7_SLCR_FPGA1_CLK_CTRL		0x0180
-#define ZY7_SLCR_FPGA2_CLK_CTRL		0x0190
-#define ZY7_SLCR_FPGA3_CLK_CTRL		0x01a0
+#define ZY7_SLCR_FPGA_CLK_CTRL(unit)	(0x0170 + 0x10*(unit))
+#define	  ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT	20
+#define	  ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK	(0x3f << 20)
+#define	  ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT	8
+#define	  ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK	(0x3f << 8)
+#define	  ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX	0x3f
+#define	  ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT	4
+#define	  ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK	(3 << 4)
+#define ZY7_SLCR_FPGA_THR_CTRL(unit)	(0x0174 + 0x10*(unit))
+#define ZY7_SLCR_FPGA_THR_CTRL_CNT_RST		(1 << 1)
+#define ZY7_SLCR_FPGA_THR_CTRL_CPU_START	(1 << 0)
+#define ZY7_SLCR_FPGA_THR_CNT(unit)	(0x0178 + 0x10*(unit))
+#define ZY7_SLCR_FPGA_THR_STA(unit)	(0x017c + 0x10*(unit))
 #define ZY7_SLCR_CLK_621_TRUE		0x01c4	/* cpu clock ratio mode */
 
 /* Reset controls. */
@@ -288,5 +296,23 @@
 extern void zy7_slcr_preload_pl(void);
 extern void zy7_slcr_postload_pl(int en_level_shifters);
 extern int cgem_set_ref_clk(int unit, int frequency);
+
+/* Should be consistent with SRCSEL field of FPGAx_CLK_CTRL */
+#define	ZY7_PL_FCLK_SRC_IO	0 
+#define	ZY7_PL_FCLK_SRC_IO_ALT	1 /* ZY7_PL_FCLK_SRC_IO is b0x */
+#define	ZY7_PL_FCLK_SRC_ARM	2
+#define	ZY7_PL_FCLK_SRC_DDR	3
+
+int zy7_pl_fclk_set_source(int unit, int source);
+int zy7_pl_fclk_get_source(int unit);
+int zy7_pl_fclk_set_freq(int unit, int freq);
+int zy7_pl_fclk_get_freq(int unit);
+int zy7_pl_fclk_enable(int unit);
+int zy7_pl_fclk_disable(int unit);
+int zy7_pl_fclk_enabled(int unit);
+int zy7_pl_level_shifters_enabled(void);
+void zy7_pl_level_shifters_enable(void);
+void zy7_pl_level_shifters_disable(void);
+
 #endif
 #endif /* _ZY7_SLCR_H_ */