From c16c8c6fd462d2c12301acaa8bfec7e98f05de6b Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Wed, 4 May 2022 13:03:38 +0200
Subject: user: Update architectures supporting TLS

---
 user/overview/index.rst | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'user')

diff --git a/user/overview/index.rst b/user/overview/index.rst
index 550724a..16389d9 100644
--- a/user/overview/index.rst
+++ b/user/overview/index.rst
@@ -355,6 +355,7 @@ sophisticated real-time applications are significantly reduced.
 
 .. [#] Thread-local storage requires some support by the tool chain and the
        RTEMS architecture support, e.g. context-switch code.  It is supported
-       at least on ARM, PowerPC, RISC-V, SPARC and m68k.  Check the
-       `RTEMS CPU Architecture Supplement <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_
-       if it is supported.
+       at least on ARM, AArch64, PowerPC, RISC-V, SPARC, MicroBlaze, Nios II,
+       and m68k.  Check the `RTEMS CPU Architecture Supplement
+       <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_ if it is
+       supported.
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