From f233256327e8a01a1236dbdd0f91701bc229936b Mon Sep 17 00:00:00 2001 From: Chris Johns Date: Fri, 7 Oct 2016 11:13:16 +1300 Subject: Clean up the CPU Supplement. --- cpu_supplement/ephiphany.rst | 45 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 23 deletions(-) (limited to 'cpu_supplement/ephiphany.rst') diff --git a/cpu_supplement/ephiphany.rst b/cpu_supplement/ephiphany.rst index ba4b4f6..fa36119 100644 --- a/cpu_supplement/ephiphany.rst +++ b/cpu_supplement/ephiphany.rst @@ -1,22 +1,28 @@ .. comment SPDX-License-Identifier: CC-BY-SA-4.0 +.. COMMENT: COPYRIGHT (c) 1988-2002. +.. COMMENT: On-Line Applications Research Corporation (OAR). +.. COMMENT: All rights reserved. + Epiphany Specific Information ############################# -This chapter discusses the`Epiphany Architecture `_ -dependencies in this port of RTEMS. Epiphany is a chip that can come with 16 and -64 cores, each of which can run RTEMS separately or they can work together to -run a SMP RTEMS application. +This chapter discusses the`Epiphany Architecture +http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of +RTEMS. Epiphany is a chip that can come with 16 and 64 cores, each of which can +run RTEMS separately or they can work together to run a SMP RTEMS application. **Architecture Documents** -For information on the Epiphany architecture refer to the`Epiphany Architecture Reference `_. +For information on the Epiphany architecture refer to the *Epiphany +Architecture Reference* http://adapteva.com/docs/epiphany_arch_ref.pdf. Calling Conventions =================== -Please refer to the`Epiphany SDK `_ -Appendix A: Application Binary Interface +Please refer to the *Epiphany SDK* +http://adapteva.com/docs/epiphany_sdk_ref.pdf Appendix A: Application Binary +Interface Floating Point Unit ------------------- @@ -26,9 +32,9 @@ A floating point unit is currently not supported. Memory Model ============ -A flat 32-bit memory model is supported, no caches. Each core has its own 32 KiB -strictly ordered local memory along with an access to a shared 32 MiB external -DRAM. +A flat 32-bit memory model is supported, no caches. Each core has its own 32 +KiB strictly ordered local memory along with an access to a shared 32 MiB +external DRAM. Interrupt Processing ==================== @@ -63,16 +69,16 @@ There are only two levels: interrupts enabled and interrupts disabled. Interrupt Stack --------------- -The Epiphany RTEMS port uses a dedicated software interrupt stack. -The stack for interrupts is allocated during interrupt driver initialization. -When an interrupt is entered, the _ISR_Handler routine is responsible for -switching from the interrupted task stack to RTEMS software interrupt stack. +The Epiphany RTEMS port uses a dedicated software interrupt stack. The stack +for interrupts is allocated during interrupt driver initialization. When an +interrupt is entered, the _ISR_Handler routine is responsible for switching +from the interrupted task stack to RTEMS software interrupt stack. Default Fatal Error Processing ============================== -The default fatal error handler for this architecture performs the -following actions: +The default fatal error handler for this architecture performs the following +actions: - disables operating system supported interrupts (IRQ), @@ -84,10 +90,3 @@ Symmetric Multiprocessing ========================= SMP is not supported. - -.. COMMENT: COPYRIGHT (c) 1988-2002. - -.. COMMENT: On-Line Applications Research Corporation (OAR). - -.. COMMENT: All rights reserved. - -- cgit v1.2.3