From 0e46b342d01fe8c4e29315288f8fc4f286d90926 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 7 Feb 2019 13:06:26 +0100 Subject: cpu-supplement: Fix file name --- cpu-supplement/ephiphany.rst | 90 -------------------------------------------- cpu-supplement/epiphany.rst | 90 ++++++++++++++++++++++++++++++++++++++++++++ cpu-supplement/index.rst | 2 +- 3 files changed, 91 insertions(+), 91 deletions(-) delete mode 100644 cpu-supplement/ephiphany.rst create mode 100644 cpu-supplement/epiphany.rst (limited to 'cpu-supplement') diff --git a/cpu-supplement/ephiphany.rst b/cpu-supplement/ephiphany.rst deleted file mode 100644 index 709dbcf..0000000 --- a/cpu-supplement/ephiphany.rst +++ /dev/null @@ -1,90 +0,0 @@ -.. SPDX-License-Identifier: CC-BY-SA-4.0 - -.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR) - -Epiphany Specific Information -***************************** - -This chapter discusses the`Epiphany Architecture -http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of -RTEMS. Epiphany is a chip that can come with 16 and 64 cores, each of which can -run RTEMS separately or they can work together to run a SMP RTEMS application. - -**Architecture Documents** - -For information on the Epiphany architecture refer to the *Epiphany -Architecture Reference* http://adapteva.com/docs/epiphany_arch_ref.pdf. - -Calling Conventions -=================== - -Please refer to the *Epiphany SDK* -http://adapteva.com/docs/epiphany_sdk_ref.pdf Appendix A: Application Binary -Interface - -Floating Point Unit -------------------- - -A floating point unit is currently not supported. - -Memory Model -============ - -A flat 32-bit memory model is supported, no caches. Each core has its own 32 -KiB strictly ordered local memory along with an access to a shared 32 MiB -external DRAM. - -Interrupt Processing -==================== - -Every Epiphany core has 10 exception types: - -- Reset - -- Software Exception - -- Data Page Fault - -- Timer 0 - -- Timer 1 - -- Message Interrupt - -- DMA0 Interrupt - -- DMA1 Interrupt - -- WANT Interrupt - -- User Interrupt - -Interrupt Levels ----------------- - -There are only two levels: interrupts enabled and interrupts disabled. - -Interrupt Stack ---------------- - -The Epiphany RTEMS port uses a dedicated software interrupt stack. The stack -for interrupts is allocated during interrupt driver initialization. When an -interrupt is entered, the _ISR_Handler routine is responsible for switching -from the interrupted task stack to RTEMS software interrupt stack. - -Default Fatal Error Processing -============================== - -The default fatal error handler for this architecture performs the following -actions: - -- disables operating system supported interrupts (IRQ), - -- places the error code in ``r0``, and - -- executes an infinite loop to simulate a halt processor instruction. - -Symmetric Multiprocessing -========================= - -SMP is not supported. diff --git a/cpu-supplement/epiphany.rst b/cpu-supplement/epiphany.rst new file mode 100644 index 0000000..709dbcf --- /dev/null +++ b/cpu-supplement/epiphany.rst @@ -0,0 +1,90 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR) + +Epiphany Specific Information +***************************** + +This chapter discusses the`Epiphany Architecture +http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of +RTEMS. Epiphany is a chip that can come with 16 and 64 cores, each of which can +run RTEMS separately or they can work together to run a SMP RTEMS application. + +**Architecture Documents** + +For information on the Epiphany architecture refer to the *Epiphany +Architecture Reference* http://adapteva.com/docs/epiphany_arch_ref.pdf. + +Calling Conventions +=================== + +Please refer to the *Epiphany SDK* +http://adapteva.com/docs/epiphany_sdk_ref.pdf Appendix A: Application Binary +Interface + +Floating Point Unit +------------------- + +A floating point unit is currently not supported. + +Memory Model +============ + +A flat 32-bit memory model is supported, no caches. Each core has its own 32 +KiB strictly ordered local memory along with an access to a shared 32 MiB +external DRAM. + +Interrupt Processing +==================== + +Every Epiphany core has 10 exception types: + +- Reset + +- Software Exception + +- Data Page Fault + +- Timer 0 + +- Timer 1 + +- Message Interrupt + +- DMA0 Interrupt + +- DMA1 Interrupt + +- WANT Interrupt + +- User Interrupt + +Interrupt Levels +---------------- + +There are only two levels: interrupts enabled and interrupts disabled. + +Interrupt Stack +--------------- + +The Epiphany RTEMS port uses a dedicated software interrupt stack. The stack +for interrupts is allocated during interrupt driver initialization. When an +interrupt is entered, the _ISR_Handler routine is responsible for switching +from the interrupted task stack to RTEMS software interrupt stack. + +Default Fatal Error Processing +============================== + +The default fatal error handler for this architecture performs the following +actions: + +- disables operating system supported interrupts (IRQ), + +- places the error code in ``r0``, and + +- executes an infinite loop to simulate a halt processor instruction. + +Symmetric Multiprocessing +========================= + +SMP is not supported. diff --git a/cpu-supplement/index.rst b/cpu-supplement/index.rst index f80373d..8de82a4 100644 --- a/cpu-supplement/index.rst +++ b/cpu-supplement/index.rst @@ -23,7 +23,7 @@ RTEMS CPU Architecture Supplement (|version|). arm atmel_avr blackfin - ephiphany + epiphany intel_amd_x86 lattice_micro32 renesas_m32c -- cgit v1.2.3