diff options
Diffstat (limited to 'user/exe/loader.rst')
| -rw-r--r-- | user/exe/loader.rst | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/user/exe/loader.rst b/user/exe/loader.rst index c11f363..fdc54a8 100644 --- a/user/exe/loader.rst +++ b/user/exe/loader.rst @@ -458,9 +458,9 @@ into the base image. .. code-block:: none - $ sparc-rtems5-gcc -mcpu=cypress foo.o -lrtemsbsp -lrtemscpu -o foo.pre - $ rtems-syms -e -C sparc-rtems5-gcc -c "-mcpu=cypress" -o foo-sym.o foo.pre - $ sparc-rtems5-gcc -mcpu=cypress foo.o foo-sym.o -lrtemsbsp -lrtemscpu -o foo.exe + $ sparc-rtems@rtems-ver-major@-gcc -mcpu=cypress foo.o -lrtemsbsp -lrtemscpu -o foo.pre + $ rtems-syms -e -C sparc-rtems@rtems-ver-major@-gcc -c "-mcpu=cypress" -o foo-sym.o foo.pre + $ sparc-rtems@rtems-ver-major@-gcc -mcpu=cypress foo.o foo-sym.o -lrtemsbsp -lrtemscpu -o foo.exe The link command line steps in this example are not complete. @@ -486,8 +486,8 @@ file. First create the symbol table's executable object file: .. code-block:: none - $ sparc-rtems5-gcc -mcpu=cypress foo.o -lrtemsbsp -lrtemscpu -o foo.exe - $ rtems-syms -C sparc-rtems5-gcc -c "-mcpu=cypress" -o foo-sym.o foo.exe + $ sparc-rtems@rtems-ver-major@-gcc -mcpu=cypress foo.o -lrtemsbsp -lrtemscpu -o foo.exe + $ rtems-syms -C sparc-rtems@rtems-ver-major@-gcc -c "-mcpu=cypress" -o foo-sym.o foo.exe The link command line steps in this example are not complete. @@ -632,7 +632,7 @@ in a library with a single command. .. code-block:: none - $ sparc-rtems5-strip libc.a + $ sparc-rtems@rtems-ver-major@-strip libc.a Large Memory ------------ @@ -837,22 +837,33 @@ Architectures The following architectures are supported: + - AArch64 - ARM - Blackfin - H8300 - Intel x86 (i386) - LM32 - M68K + - MicroBlaze - MIPS - Moxie - PowerPC - SPARC - V850 +AArch64 +^^^^^^^ + +The AArch64 relocation backend supports veneers which is trampolines. + +The veneer implementation is two instructions and a 64bit target address +making the overhead 16 bytes for each veneer. The performance overhead is two +instructions. + ARM ^^^ -The ARM relocation backend supports veneers which is trampolines. +The ARM relocation backend supports veneers. The veneer implementation is a single instruction and a 32bit target address making the overhead 8 bytes for each veneer. The performance overhead is a |