diff options
Diffstat (limited to 'user/bsps/aarch64')
| -rw-r--r-- | user/bsps/aarch64/raspberrypi4.rst | 109 | ||||
| -rw-r--r-- | user/bsps/aarch64/xilinx-zynqmp.rst | 66 |
2 files changed, 162 insertions, 13 deletions
diff --git a/user/bsps/aarch64/raspberrypi4.rst b/user/bsps/aarch64/raspberrypi4.rst new file mode 100644 index 0000000..efb09b6 --- /dev/null +++ b/user/bsps/aarch64/raspberrypi4.rst @@ -0,0 +1,109 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +.. Copyright (C) 2022 Mohd Noor Aman + +.. _BSP_aarch64_Raspberrypi_4: + +Raspberry Pi 4B +=============== + +The 'raspberrypi4b' BSP currently supports only the LP64 ABI. ILP32 is not +supported. Raspberry pi 4B all variants and Raspberry Pi 400 are supported. The +default bootloader which is used by the Raspbian OS or other OS can be used to +boot RTEMS. SMP is currently not supported. + +Raspberry Pi 4B has 2 types of interrupt controller, GIC-400 (GICv2) and ARM +legacy generic controller. Both are supported. By default, raspberrypi 4B uses +ARM legacy generic controller. Set ``enable_gic=1`` in the ``config.txt`` file +to enable GIC. + +Clock Driver +------------ + +The clock driver uses the `ARM Generic Timer`. + +Console Driver +-------------- + +Raspberry pi 4B has 2 types of UARTs, ARM PL011 and Mini-uart. The PL011 is a +capable, broadly 16550-compatible UART, while the mini UART has a reduced +feature set. The console driver supports the default Qemu emulated ARM PL011 +PrimeCell UART as well as the physical ARM PL011 PrimeCell UART in the +raspberrypi hardware. Mini-uart is not supported. + +Preparing to boot +------------------ + +Raspberry Pi uses a different mechanism to boot when compared with any ARM SoC. +First the GPU initializes, loads the bootloader (Raspberry pi firmware) and then +looks for the kernel img. This whole process is done by the GPU (VideoCore IV) +till the kernel is loaded. More information can be found on the `Raspberry pi +documentation page +<https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#boot-sequence>`_. +By default the arm64 mode looks for the ``kernel8.img``. Any other kernel can be +loaded by adding ``kernel=<img_name>`` to the ``config.txt`` file. + +The Firmware files are required in order to boot RTEMS. The latest firmware can +be downloaded from the `Raspberry Pi Firmware Repository +<https://github.com/raspberrypi/firmware/>`_. USB boot is supported. All the +files (Firmwares and kernel) must be place in the FAT32 partition only. Add +``arm_64bit=1`` in the ``config.txt`` file in order to boot the BSP in 64bit +kernel mode. + + +UART Setup +^^^^^^^^^^ + +Connect your serial device to the GPIO15 and GPIO14. Add the following to the +``config.txt`` file in order to use the PL011 UART0 and thus disabling the +default Mini-uart. + +.. code-block:: none + + # if user wants to enable GIC, uncomment the next line + # enable_gic=1 + arm_64bit=1 + dtoverlay = disable-bt + enable_uart=1 + +.. note:: + The Raspberry Pi 4B and 400 have an additional four PL011 UARTs. They are not + supported. + +Generating kernel image +^^^^^^^^^^^^^^^^^^^^^^^ + +The following steps show how to run ``hello.exe`` on the BSP. Other executables +can be processed in a similar way. + +To create the kernel image: + +.. code-block:: shell + + $ aarch64-rtems@rtems-ver-major@-objcopy -Obinary hello.exe kernel8.img + +Copy the kernel image to the SD card. + +JTAG Setup +---------- + +The Raspberry Pi 4 doesn't have dedicated JTAG pins. Instead, you must configure +the GPIO pins (GPIO22-GPIO27) to activate the JTAG functionality. The RPi 4 +documentation refers to this as Alt4 functions of those pins. Alt5 does exist +too, which goes from GPIO4, 5, 6, 12 and 13. you can check this out from +`pinout.xyz <https://pinout.xyz/pinout/jtag#>`_ or `eLinux +<https://elinux.org/RPi_BCM2835_GPIOs>`_ + +One more thing to note on JTAG with Raspberry pi 4B is that, by default, All the +GPIO pins are pulled down, according to the `BCM2711 documentation +<https://datasheets.raspberrypi.com/bcm2711/bcm2711-peripherals.pdf>`_. This +wasn't the case in the earlier models. So in order to let the data flow freely, +we will have to disable them. + +.. code-block:: none + + # Disable pull downs + gpio=22-27=np + + # Enable jtag pins (i.e. GPIO22-GPIO27) + enable_jtag_gpio=1 diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst b/user/bsps/aarch64/xilinx-zynqmp.rst index 78bff12..4de0115 100644 --- a/user/bsps/aarch64/xilinx-zynqmp.rst +++ b/user/bsps/aarch64/xilinx-zynqmp.rst @@ -6,19 +6,39 @@ .. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_qemu: .. _BSP_aarch64_qemu_xilinx_zynqmp_ilp32_zu3eg: .. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_zu3eg: +.. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_cfc400x: Qemu Xilinx ZynqMP ================== -This BSP supports four variants: `xilinx-zynqmp-ilp32-qemu`, -`xilinx-zynqmp-lp64-qemu`, `xilinx-zynqmp-ilp32-zu3eg`, and -`xilinx-zynqmp-lp64-zu3eg`. Platform-specific hardware initialization is -performed by ARM Trusted Firmware (ATF). Other basic hardware initialization is -performed by the BSP. These BSPs support the GICv2 interrupt controller present -in all ZynqMP systems. The zu3eg BSPs have also been tested to be fully -functional on zu2cg boards and should also work on any other ZynqMP chip variant -since the Processing Subsystem (PS) does not vary among chip variants other than -the number of CPU cores available. +This BSP family supports the following variants: + +* `xilinx-zynqmp-ilp32-qemu` + +* `xilinx-zynqmp-lp64-qemu` + +* `xilinx-zynqmp-ilp32-zu3eg` + +* `xilinx-zynqmp-lp64-zu3eg` + +* `xilinx-zynqmp-lp64-cfc400x` + +Platform-specific hardware initialization is performed by ARM Trusted Firmware +(ATF). Other basic hardware initialization is performed by the BSP. These BSPs +support the GICv2 interrupt controller present in all ZynqMP systems. The zu3eg +BSPs have also been tested to be fully functional on zu2cg boards and should +also work on any other ZynqMP chip variant since the Processing Subsystem (PS) +does not vary among chip variants other than the number of CPU cores available. + +This BSP family has been tested on the following hardware: + +* `Avnet UltraZed-EG SOM` + +* `Innoflight CFC-400X` + +* `Trenz TE0802` + +* `Xilinx ZCU102` Boot on QEMU ------------ @@ -33,6 +53,14 @@ will drop to EL1 for execution. For quick turnaround during testing, it is recommended to use the u-boot BOOT.bin that comes with the PetaLinux prebuilts for the board in question. +Some systems such as the CFC-400X may require a bitstream to be loaded into the +FPGA portion of the chip to operate as expected. This bitstream must be loaded +before RTEMS begins operation since accesses to programmable logic (PL) memory +space can cause the CPU to hang if the FPGA is not initialized. This can be +performed as part of BOOT.bin or by a bootloader such as u-boot. Loading +bitstreams from RTEMS has not been tested on the ZynqMP platform and requires +additional libraries from Xilinx. + Hardware Boot Image Generation ------------------------------ @@ -116,7 +144,7 @@ Prepare your RTEMS image to boot from u-boot with the following commands: .. code-block:: shell - $ aarch64-rtems6-objcopy -Obinary ticker.exe ticker.bin + $ aarch64-rtems@rtems-ver-major@-objcopy -Obinary ticker.exe ticker.bin $ gzip -9 ticker.bin $ mkimage -A arm64 -O rtems -T kernel -a 0x10000000 -e 0x10000000 -n RTEMS -d ticker.bin.gz rtems.img @@ -179,7 +207,7 @@ This is the entire boot sequence: ## Transferring control to RTEMS (at address 10000000) ... *** BEGIN OF TEST CLOCK TICK *** - *** TEST VERSION: 6.0.0.f381e9bab29278e4434b1a93e70d17a7562dc64c + *** TEST VERSION: @rtems-version@.f381e9bab29278e4434b1a93e70d17a7562dc64c *** TEST STATE: EXPECTED_PASS *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP *** TEST TOOLS: 10.3.1 20210409 (RTEMS 6, RSB ad54d1dd3cf8249d9d39deb1dd28b2f294df062d, Newlib eb03ac1) @@ -225,7 +253,7 @@ as well as the physical ARM PL011 PrimeCell UART in the ZynqMP hardware. SDHCI Driver ------------ -The ZynqMP bsp has an SDHCI driver which allows reading to and writing from SD +The ZynqMP bsp has an SDHCI driver which allows writing to and reading from SD cards. These can be tested in qemu using the "-sd" option. For example: .. code-block:: shell @@ -242,7 +270,19 @@ Network Configuration When used with LibBSD, these BSP variants support networking via the four Cadence GEM instances present on all ZynqMP hardware variants. All interfaces are enabled by default, but only interfaces with operational MII busses will be -recognized and usable in RTEMS. Most ZynqMP dev boards use CGEM3. +recognized and usable in RTEMS. Most ZynqMP dev boards use RGMII with CGEM3. + +When used with lwIP from the rtems-lwip integration repository, these BSP +variants support networking via CGEM0 and one of the other CGEM* instances +simultaneously. This is a limitation of the Xilinx driver, specifically +in code referring directly to XPAR_XEMACPS_0_BASEADDR. Attempting to use more +than two interfaces simultaneously may cause unexpected behavior. Attempting to +use a set of two interfaces that does not include CGEM0 may cause unexpected +behavior. + +The interfaces will not come up by default under lwIP and must be configured +manually. There are examples of this in the start_networking() implementation +in netstart.c as used by the network tests. Running Executables on QEMU --------------------------- |