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diff --git a/cpu_supplement/arm.rst b/cpu_supplement/arm.rst index 05dda39..64fc156 100644 --- a/cpu_supplement/arm.rst +++ b/cpu_supplement/arm.rst @@ -1,31 +1,37 @@ .. comment SPDX-License-Identifier: CC-BY-SA-4.0 +.. COMMENT: COPYRIGHT (c) 1988-2009. +.. COMMENT: On-Line Applications Research Corporation (OAR). +.. COMMENT: All rights reserved. + ARM Specific Information ######################## -This chapter discusses the`ARM architecture <http://en.wikipedia.org/wiki/ARM_architecture>`_ -dependencies in this port of RTEMS. The ARMv4T (and compatible), ARMv7-A, -ARMv7-R and ARMv7-M architecture versions are supported by RTEMS. Processors -with a MMU use a static configuration which is set up during system start. SMP -is supported. +This chapter discusses the *ARM architecture* +(http://en.wikipedia.org/wiki/ARM_architecture) dependencies in this port of +RTEMS. The ARMv4T (and compatible), ARMv7-A, ARMv7-R and ARMv7-M architecture +versions are supported by RTEMS. Processors with a MMU use a static +configuration which is set up during system start. SMP is supported. **Architecture Documents** -For information on the ARM architecture refer to the`ARM Infocenter <http://infocenter.arm.com>`_. +For information on the ARM architecture refer to the *ARM Infocenter* +(http://infocenter.arm.com/). CPU Model Dependent Features ============================ -This section presents the set of features which vary -across ARM implementations and are of importance to RTEMS. The set of CPU -model feature macros are defined in the file:file:`cpukit/score/cpu/arm/rtems/score/arm.h` based upon the particular CPU -model flags specified on the compilation command line. +This section presents the set of features which vary across ARM implementations +and are of importance to RTEMS. The set of CPU model feature macros are +defined in the file :file:`cpukit/score/cpu/arm/rtems/score/arm.h` based upon +the particular CPU model flags specified on the compilation command line. CPU Model Name -------------- -The macro ``CPU_MODEL_NAME`` is a string which designates -the architectural level of this CPU model. See in:file:`cpukit/score/cpu/arm/rtems/score/arm.h` for the values. +The macro ``CPU_MODEL_NAME`` is a string which designates the architectural +level of this CPU model. See in :file:`cpukit/score/cpu/arm/rtems/score/arm.h` +for the values. Count Leading Zeroes Instruction -------------------------------- @@ -51,32 +57,32 @@ Multilibs The following multilibs are available: -# ``.``: ARMv4T, ARM instruction set +#. ``.``: ARMv4T, ARM instruction set -# ``thumb``: ARMv4T, Thumb-1 instruction set +#. ``thumb``: ARMv4T, Thumb-1 instruction set -# ``thumb/armv6-m``: ARMv6M, subset of Thumb-2 instruction set +#. ``thumb/armv6-m``: ARMv6M, subset of Thumb-2 instruction set -# ``thumb/armv7-a``: ARMv7-A, Thumb-2 instruction set +#. ``thumb/armv7-a``: ARMv7-A, Thumb-2 instruction set -# ``thumb/armv7-a/neon/hard``: ARMv7-A, Thumb-2 instruction set with - hard-float ABI Neon and VFP-D32 support +#. ``thumb/armv7-a/neon/hard``: ARMv7-A, Thumb-2 instruction set with + hard-float ABI Neon and VFP-D32 support -# ``thumb/armv7-r``: ARMv7-R, Thumb-2 instruction set +#. ``thumb/armv7-r``: ARMv7-R, Thumb-2 instruction set -# ``thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Thumb-2 instruction set - with hard-float ABI VFP-D16 support +#. ``thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Thumb-2 instruction set with + hard-float ABI VFP-D16 support -# ``thumb/armv7-m``: ARMv7-M, Thumb-2 instruction set with hardware - integer division (SDIV/UDIV) +#. ``thumb/armv7-m``: ARMv7-M, Thumb-2 instruction set with hardware + integer division (SDIV/UDIV) -# ``thumb/armv7-m/fpv4-sp-d16``: ARMv7-M, Thumb-2 instruction set with - hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support +#. ``thumb/armv7-m/fpv4-sp-d16``: ARMv7-M, Thumb-2 instruction set with + hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support -# ``eb/thumb/armv7-r``: ARMv7-R, Big-endian Thumb-2 instruction set +#. ``eb/thumb/armv7-r``: ARMv7-R, Big-endian Thumb-2 instruction set -# ``eb/thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Big-endian Thumb-2 - instruction set with hard-float ABI VFP-D16 support +#. ``eb/thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Big-endian Thumb-2 instruction + set with hard-float ABI VFP-D16 support Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets. @@ -93,15 +99,17 @@ Multilib 4. and 5. support the Cortex-A processors. Multilib 6., 7., 10. and 11. support the Cortex-R processors. Here also big-endian variants are available. -Use for example the following GCC options -.. code:: c +Use for example the following GCC options: + +.. code-block:: shell -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 to build an application or BSP for the ARMv7-A architecture and tune the code for a Cortex-A9 processor. It is important to select the options used for the -multilibs. For example -.. code:: c +multilibs. For example: + +.. code-block:: shell -mthumb -mcpu=cortex-a9 @@ -110,7 +118,8 @@ alone will not select the ARMv7-A multilib. Calling Conventions =================== -Please refer to the`Procedure Call Standard for the ARM Architecture <http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf>`_. +Please refer to the *Procedure Call Standard for the ARM Architecture* +(http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf). Memory Model ============ @@ -143,13 +152,13 @@ operating system support for the FIQ it is not necessary to disable them during critical sections of the system. The ARMv7-M architecture has a completely different exception model. Here -interrupts are disabled with a write of 0x80 to the ``basepri_max`` -register. This means that all exceptions and interrupts with a priority value -of greater than or equal to 0x80 are disabled. Thus exceptions and interrupts -with a priority value of less than 0x80 are non-maskable with respect to the -operating system and therefore must not use operating system services. Several -support libraries of chip vendors implicitly shift the priority value somehow -before the value is written to the NVIC IPR register. This can easily lead to +interrupts are disabled with a write of 0x80 to the ``basepri_max`` register. +This means that all exceptions and interrupts with a priority value of greater +than or equal to 0x80 are disabled. Thus exceptions and interrupts with a +priority value of less than 0x80 are non-maskable with respect to the operating +system and therefore must not use operating system services. Several support +libraries of chip vendors implicitly shift the priority value somehow before +the value is written to the NVIC IPR register. This can easily lead to confusion. Interrupt Levels @@ -168,8 +177,8 @@ the stacks is usually reserved in the linker script. Default Fatal Error Processing ============================== -The default fatal error handler for this architecture performs the -following actions: +The default fatal error handler for this architecture performs the following +actions: - disables operating system supported interrupts (IRQ), @@ -187,10 +196,3 @@ Thread-Local Storage ==================== Thread-local storage is supported. - -.. COMMENT: COPYRIGHT (c) 1988-2009. - -.. COMMENT: On-Line Applications Research Corporation (OAR). - -.. COMMENT: All rights reserved. - |