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Diffstat (limited to 'cpu-supplement')
| -rw-r--r-- | cpu-supplement/index.rst | 1 | ||||
| -rw-r--r-- | cpu-supplement/riscv.rst | 79 |
2 files changed, 80 insertions, 0 deletions
diff --git a/cpu-supplement/index.rst b/cpu-supplement/index.rst index 002c206..1d810a2 100644 --- a/cpu-supplement/index.rst +++ b/cpu-supplement/index.rst @@ -56,6 +56,7 @@ to the Community Project hosted at http://www.rtems.org/. altera_nios_ii openrisc_1000 powerpc + riscv superh sparc sparc64 diff --git a/cpu-supplement/riscv.rst b/cpu-supplement/riscv.rst new file mode 100644 index 0000000..9ed5e32 --- /dev/null +++ b/cpu-supplement/riscv.rst @@ -0,0 +1,79 @@ +.. comment SPDX-License-Identifier: CC-BY-SA-4.0 + +.. COMMENT: Copyright (c) 2018 +.. COMMENT: embedded brains GmbH +.. COMMENT: All rights reserved. + +RISC-V Specific Information +*************************** + +Calling Conventions +=================== + +Please refer to the +`RISC-V ELF psABI specification <https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md>`_. + +Multilibs +========= + +The GCC for RISC-V can generate code for several 32-bit and 64-bit ISA/ABI +variants. The following multilibs are available: + +* ``.``: The default multilib ISA is RV32IMAFDC with ABI ILP32D. + +* ``rv32i/ilp32``: ISA RV32I with ABI ILP32. + +* ``rv32im/ilp32``: ISA RV32IM with ABI ILP32. + +* ``rv32imafd/ilp32d``: ISA RV32IMAFD with ABI ILP32D. + +* ``rv32iac/ilp32``: ISA RV32IAC with ABI ILP32. + +* ``rv32imac/ilp32``: ISA RV32IMAC with ABI ILP32. + +* ``rv32imafc/ilp32f``: ISA RV32IMAFC with ABI ILP32F. + +* ``rv64imafd/lp64d``: ISA RV64IMAFD with ABI LP64D and code model medlow. + +* ``rv64imafd/lp64d/medany``: ISA RV64IMAFD with ABI LP64D and code model medany. + +* ``rv64imac/lp64``: ISA RV64IMAC with ABI LP64 and code model medlow. + +* ``rv64imac/lp64/medany``: ISA RV64IMAC with ABI LP64 and code model medany. + +* ``rv64imafdc/lp64d``: ISA RV64IMAFDC with ABI LP64D and code model medlow. + +* ``rv64imafdc/lp64d/medany``: ISA RV64IMAFDC with ABI LP64D and code model medany. + +Interrupt Processing +==================== + +Interrupt exceptions are handled via the interrupt extensions API. All other +exceptions end up in a fatal error (RTEMS_FATAL_SOURCE_EXCEPTION). + +Interrupt Levels +---------------- + +There are exactly two interrupt levels on RISC-V with respect to RTEMS. Level +zero corresponds to machine interrupts enabled. Level one corresponds to +machine interrupts disabled. + +Interrupt Stack +--------------- + +The memory region for the interrupt stack is defined by the BSP. + +Default Fatal Error Processing +============================== + +The default fatal error is BSP-specific. + +Symmetric Multiprocessing +========================= + +SMP is supported. + +Thread-Local Storage +==================== + +Thread-local storage is supported. |