diff options
| -rw-r--r-- | cpu-supplement/sparc.rst | 27 | ||||
| -rw-r--r-- | rsb/third-party-packages.rst | 2 | ||||
| -rw-r--r-- | user/installation/releases.rst | 2 |
3 files changed, 7 insertions, 24 deletions
diff --git a/cpu-supplement/sparc.rst b/cpu-supplement/sparc.rst index bb94435..e0f5240 100644 --- a/cpu-supplement/sparc.rst +++ b/cpu-supplement/sparc.rst @@ -35,7 +35,7 @@ available from SPARC International, Inc. (http://www.sparc.com): **ERC32 Specific Information** -The European Space Agency's ERC32 is a three chip computing core implementing a +The European Space Agency's ERC32 is a microprocessor implementing a SPARC V7 processor and associated support circuitry for embedded space applications. The integer and floating-point units (90C601E & 90C602E) are based on the Cypress 7C601 and 7C602, with additional error-detection and @@ -46,28 +46,11 @@ error-detection. The core is designed to work at 25MHz, but using space qualified memories limits the system frequency to around 15 MHz, resulting in a performance of 10 MIPS and 2 MFLOPS. -Information on the ERC32 and a number of development support tools, such as the -SPARC Instruction Simulator (SIS), are freely available on the Internet. The -following documents and SIS are available via anonymous ftp or pointing your -web browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. +The ERC32 is available from Atmel as the TSC695F. -- ERC32 System Design Document - -- MEC Device Specification - -Additionally, the SPARC RISC User's Guide from Matra MHS documents the -functionality of the integer and floating point units including the instruction -set information. To obtain this document as well as ERC32 components and VHDL -models contact: - - Matra MHS SA - 3 Avenue du Centre, BP 309, - 78054 St-Quentin-en-Yvelines, - Cedex, France - VOICE: +31-1-30607087 - FAX: +31-1-30640693 - -Amar Guennon (amar.guennon@matramhs.fr) is familiar with the ERC32. +The RTEMS configuration of GDB enables the SPARC Instruction Simulator (SIS) +which can simulate the ERC32 as well as the follow up LEON2 and LEON3 +microprocessors. CPU Model Dependent Features ============================ diff --git a/rsb/third-party-packages.rst b/rsb/third-party-packages.rst index a43abeb..21d9887 100644 --- a/rsb/third-party-packages.rst +++ b/rsb/third-party-packages.rst @@ -46,7 +46,7 @@ To build Net-SNMP the command is: $ ../source-builder/sb-set-builder --log=log_sis_net_snmp \ --prefix=$HOME/development/rtems/bsps/4.11 \ --with-tools=$HOME/development/rtems/4.11 \ - --host=sparc-rtems4.11 --with-rtems-bsp=sis 4.11/net-mgmt/net-snmp + --host=sparc-rtems4.11 --with-rtems-bsp=erc32 4.11/net-mgmt/net-snmp RTEMS Source Builder - Set Builder, v0.3.0 Build Set: 4.11/net-mgmt/net-snmp config: net-mgmt/net-snmp-5.7.2.1-1.cfg diff --git a/user/installation/releases.rst b/user/installation/releases.rst index 92fce78..afce803 100644 --- a/user/installation/releases.rst +++ b/user/installation/releases.rst @@ -54,7 +54,7 @@ shosted here. It has excellent internet access and performance. By default all the BSPs for an architecture are built. If you only wish to have a specific BSP built you can specify the BSP list by providing to the RSB the option ``--with-rtemsbsp``. For example to build two BSPs for the - SPARC architecture you can supply ``--with-rtemsbsp="erc32 sis"``. This can + SPARC architecture you can supply ``--with-rtemsbsp="erc32 leon3"``. This can speed the build time up for some architectures that have a lot of BSPs. Once you have built the tools and kernel you can move to the Packages section |