diff options
Diffstat (limited to '')
| -rw-r--r-- | bsp-howto/clock.rst | 34 | ||||
| -rw-r--r-- | user/bsps/arm/xilinx-zynqmp-rpu.rst | 35 |
2 files changed, 49 insertions, 20 deletions
diff --git a/bsp-howto/clock.rst b/bsp-howto/clock.rst index 043083f..ed83472 100644 --- a/bsp-howto/clock.rst +++ b/bsp-howto/clock.rst @@ -139,6 +139,9 @@ Simple Timecounter Variant For an example see the `ERC32 clock driver <https://git.rtems.org/rtems/tree/bsps/sparc/erc32/clock/ckinit.c>`_. +The argument parameter of ``Clock_driver_timecounter_tick( arg )`` is the +argument used to install the clock interrupt handler. Device drivers may use +this argument to access their control state. .. code-block:: c @@ -165,9 +168,9 @@ For an example see the `ERC32 clock driver ); } - static void some_tc_tick( void ) + static void some_tc_tick( rtems_timecounter_simple *tc ) { - rtems_timecounter_simple_downcounter_tick( &some_tc, some_tc_get ); + rtems_timecounter_simple_downcounter_tick( tc, some_tc_get ); } static void some_support_initialize_hardware( void ) @@ -193,8 +196,8 @@ For an example see the `ERC32 clock driver #define Clock_driver_support_initialize_hardware() \ some_support_initialize_hardware() - #define Clock_driver_timecounter_tick() \ - some_tc_tick() + #define Clock_driver_timecounter_tick( arg ) \ + some_tc_tick( arg ) #include "../../../shared/dev/clock/clockimpl.h" @@ -224,15 +227,20 @@ Install Clock Tick Interrupt Service Routine ============================================ The clock driver may provide a function to install the clock tick interrupt -service routine via ``Clock_driver_support_install_isr()``. The clock tick -interrupt service routine is passed as the one and only parameter to this -macro. The default implementation will do nothing. +service routine via ``Clock_driver_support_install_isr( isr )``. The clock +tick interrupt service routine is passed as the one and only parameter to this +macro. The default implementation will do nothing. The argument parameter (in +the code below ``&some_instance``) for the installed interrupt handler is +available in the ``Clock_driver_support_at_tick( arg )`` and +``Clock_driver_support_initialize_hardware( arg )`` customization macros. .. code-block:: c #include <bsp/irq.h> #include <bsp/fatal.h> + static some_control some_instance; + static void some_support_install_isr( rtems_interrupt_handler isr ) { rtems_status_code sc; @@ -241,7 +249,7 @@ macro. The default implementation will do nothing. "Clock", RTEMS_INTERRUPT_UNIQUE, isr, - NULL + &some_instance ); if ( sc != RTEMS_SUCCESSFUL ) { bsp_fatal( SOME_FATAL_IRQ_INSTALL ); @@ -257,17 +265,19 @@ Support At Tick =============== The hardware-specific support at tick is specified by -``Clock_driver_support_at_tick()``. +``Clock_driver_support_at_tick( arg )``. The ``arg`` is the argument used to +install the clock interrupt handler. Device drivers may use this argument to +access their control state. .. code-block:: c - static void some_support_at_tick( void ) + static void some_support_at_tick( some_control *arg ) { /* Clear interrupt */ } - #define Clock_driver_support_at_tick() \ - some_support_at_tick() + #define Clock_driver_support_at_tick( arg ) \ + some_support_at_tick( arg ) #include "../../../shared/dev/clock/clockimpl.h" diff --git a/user/bsps/arm/xilinx-zynqmp-rpu.rst b/user/bsps/arm/xilinx-zynqmp-rpu.rst index a29cb84..0dfb77e 100644 --- a/user/bsps/arm/xilinx-zynqmp-rpu.rst +++ b/user/bsps/arm/xilinx-zynqmp-rpu.rst @@ -35,14 +35,13 @@ it is recommended to use Cortex-A53 u-boot to avoid repeated BOOT.bin generation since the provided Cortex-R5 u-boot is highly limited and has no network or MMC/SD access. -Note that if the RPU image is started by the Cortex-A53 u-boot, the BSP -configuration must be updated to move ZYNQMP_RPU_RAM_INT_0_ORIGIN and -ZYNQMP_RPU_RAM_INT_1_ORIGIN into DDR since the TCMs are not directly available -to the Cortex-A53 cores at their Cortex-R5 internal addresses. Alternatively, -those sections could be copied to the TCMs using their global addresses, but -this must be done using additional commands within u-boot. If this is not taken -into account, the Cortex-R5 CPU will fail to boot correctly since execution -will jump into uninitialized TCM. +Note that if the RPU image is started by the Cortex-A53 u-boot, the program +sections located at ZYNQMP_RPU_RAM_INT_0_ORIGIN and ZYNQMP_RPU_RAM_INT_1_ORIGIN +must be manually relocated from DDR to TCM since the TCMs are not directly +available to the Cortex-A53 cores at their Cortex-R5 internal addresses. This +can be accomplished by disabling dcache in u-boot and using u-boot's "cp" +command. Once this is done, the program can be started at 0x0 by using u-boot's +"cpu" command to first disable core 4 and then release it in split mode. Hardware Boot Image Generation ------------------------------ @@ -74,3 +73,23 @@ following command: -device loader,addr=0xff9a0000,data=0x80000218,data-len=4 \ -hw-dtb /xlnx-qemu-devtrees-path/LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \ -m 4096 -display none + +Debugging Executables on QEMU +----------------------------- + +Debugging the RPU cores under QEMU presents unique challenges due to requiring +the AArch64 QEMU to emulate the entire processing subsystem. Debugging requires +a multi-arch GDB which can be created by adding "--enable-targets=all" to the +normal GDB configure line and then building as normal. + +To attach to the RPU core once QEMU is started with "-s -S", The following steps +are required: + +.. code-block:: shell + + aarch64-rtems6-gdb + (gdb) tar ext :1234 + (gdb) add-inferior + (gdb) inferior 2 + (gdb) file example.exe + (gdb) attach 2 |