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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-05-04 13:03:38 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-05-04 13:04:15 +0200 |
commit | c16c8c6fd462d2c12301acaa8bfec7e98f05de6b (patch) | |
tree | 21c6c2cfd476ddb026c1ac5f94f3a98b73e14eb9 /user | |
parent | user/bsps/arm: remove dangling stm32h7 bsp page (diff) | |
download | rtems-docs-c16c8c6fd462d2c12301acaa8bfec7e98f05de6b.tar.bz2 |
user: Update architectures supporting TLS
Diffstat (limited to 'user')
-rw-r--r-- | user/overview/index.rst | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/user/overview/index.rst b/user/overview/index.rst index 550724a..16389d9 100644 --- a/user/overview/index.rst +++ b/user/overview/index.rst @@ -355,6 +355,7 @@ sophisticated real-time applications are significantly reduced. .. [#] Thread-local storage requires some support by the tool chain and the RTEMS architecture support, e.g. context-switch code. It is supported - at least on ARM, PowerPC, RISC-V, SPARC and m68k. Check the - `RTEMS CPU Architecture Supplement <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_ - if it is supported. + at least on ARM, AArch64, PowerPC, RISC-V, SPARC, MicroBlaze, Nios II, + and m68k. Check the `RTEMS CPU Architecture Supplement + <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_ if it is + supported. |