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| author | Ryan Long <ryan.long@oarcorp.com> | 2022-08-08 15:04:29 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-08-12 10:04:24 -0500 |
| commit | 1c17ec45f837b0f858042cc28379b9432ac368c1 (patch) | |
| tree | 94f00e1227d840930526aa385e724ac1b1fe9ba4 /user/exe/loader.rst | |
| parent | pdf: Set TEXINPUTS to the tex source path (diff) | |
| download | rtems-docs-1c17ec45f837b0f858042cc28379b9432ac368c1.tar.bz2 | |
loader.rst: Add documentation for AArch64 support
Diffstat (limited to '')
| -rw-r--r-- | user/exe/loader.rst | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/user/exe/loader.rst b/user/exe/loader.rst index de77343..be2e78e 100644 --- a/user/exe/loader.rst +++ b/user/exe/loader.rst @@ -837,6 +837,7 @@ Architectures The following architectures are supported: + - AArch64 - ARM - Blackfin - H8300 @@ -849,10 +850,19 @@ The following architectures are supported: - SPARC - V850 +AArch64 +^^^^^^^ + +The AArch64 relocation backend supports veneers which is trampolines. + +The veneer implementation is two instructions and a 64bit target address +making the overhead 16 bytes for each veneer. The performance overhead is two +instructions. + ARM ^^^ -The ARM relocation backend supports veneers which is trampolines. +The ARM relocation backend supports veneers. The veneer implementation is a single instruction and a 32bit target address making the overhead 8 bytes for each veneer. The performance overhead is a |