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author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2020-12-07 11:01:47 -0600 |
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committer | Joel Sherrill <joel@rtems.org> | 2020-12-11 17:16:01 -0600 |
commit | 265bee75ec9a4fb89d104781bdf4628e8d5ca256 (patch) | |
tree | 8ca54fbe4216d9c631cc448dd17105769a7b70fc /user/bsps/aarch64/xilinx-zynqmp.rst | |
parent | user: Add A53 Qemu run instructions (diff) | |
download | rtems-docs-265bee75ec9a4fb89d104781bdf4628e8d5ca256.tar.bz2 |
user: Add aarch64/xilinx-zynqmp
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-rw-r--r-- | user/bsps/aarch64/xilinx-zynqmp.rst | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst b/user/bsps/aarch64/xilinx-zynqmp.rst new file mode 100644 index 0000000..fd225b5 --- /dev/null +++ b/user/bsps/aarch64/xilinx-zynqmp.rst @@ -0,0 +1,35 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +.. Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + +.. _BSP_aarch64_qemu_xilinx_zynqmp_ilp32: +.. _BSP_aarch64_qemu_xilinx_zynqmp_lp64: + +Qemu Xilinx ZynqMP +================== + +This BSP supports two variants, `xilinx-zynqmp-ilp32` and `xilinx-zynqmp-lp64`. +The basic hardware initialization is performed by the BSP. These BSPs support +the GICv2 interrupt controller present in all ZynqMP systems. + +Boot via ELF +------------ +The executable image is booted by Qemu in ELF format. + +Clock Driver +------------ + +The clock driver uses the `ARM Generic Timer`. + +Console Driver +-------------- + +The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART. + +Running Executables +------------------- + +Executables generated by these BSPs can be run using the following command:: + +qemu-system-aarch64 -no-reboot -nographic -serial null -serial mon:stdio \ + -machine xlnx-zcu102 -m 4096 -kernel example.exe |