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| author | Amar Takhar <amar@rtems.org> | 2016-01-18 00:37:40 -0500 |
|---|---|---|
| committer | Amar Takhar <verm@darkbeer.org> | 2016-05-02 20:51:24 -0400 |
| commit | d389819eea3a84e388935153e3be847342809da3 (patch) | |
| tree | 15cfe55f41281cead805ce87f66c5d7248caa9ce /porting/miscellanous.rst | |
| parent | Remove ada_user document. (diff) | |
| download | rtems-docs-d389819eea3a84e388935153e3be847342809da3.tar.bz2 | |
Convert all Unicode to ASCII(128)
Diffstat (limited to 'porting/miscellanous.rst')
| -rw-r--r-- | porting/miscellanous.rst | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/porting/miscellanous.rst b/porting/miscellanous.rst index 9bbd712..01073f7 100644 --- a/porting/miscellanous.rst +++ b/porting/miscellanous.rst @@ -5,7 +5,7 @@ Fatal Error Default Handler =========================== The ``_CPU_Fatal_halt`` routine is the default fatal error handler. This -routine copies _error into a known place – typically a stack location or +routine copies _error into a known place - typically a stack location or a register, optionally disables interrupts, and halts/stops the CPU. It is prototyped as follows and is often implemented as a macro: .. code:: c @@ -100,8 +100,8 @@ single instruction (e.g. i486). It is probably best to avoid an "endian swapping control bit" in the CPU. One good reason is that interrupts would probably have to be disabled to insure that an interrupt does not try to access the same "chunk" with the wrong endian. Another good reason -is that on some CPUs, the endian bit endianness for ALL fetches – both -code and data – so the code will be fetched incorrectly. +is that on some CPUs, the endian bit endianness for ALL fetches - both +code and data - so the code will be fetched incorrectly. The following is an implementation of the ``CPU_swap_u32`` routine that will work on any CPU. It operates by breaking the unsigned thirty-two bit @@ -142,8 +142,8 @@ single instruction (e.g. i486). It is probably best to avoid an "endian swapping control bit" in the CPU. One good reason is that interrupts would probably have to be disabled to insure that an interrupt does not try to access the same "chunk" with the wrong endian. Another good reason -is that on some CPUs, the endian bit endianness for ALL fetches – both -code and data – so the code will be fetched incorrectly. +is that on some CPUs, the endian bit endianness for ALL fetches - both +code and data - so the code will be fetched incorrectly. Similarly, here is a portable implementation of the ``CPU_swap_u16`` routine. Just as with the ``CPU_swap_u32`` routine, the porter |