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authorJoel Sherrill <joel@rtems.org>2016-10-28 13:07:04 -0500
committerJoel Sherrill <joel@rtems.org>2016-10-28 13:10:22 -0500
commit0c978901d082c88a74f269ddf184438300c58213 (patch)
tree42919a9cc0036deb544dc7b0216f6920c72009cf /cpu_supplement/sparc.rst
parent23a5ce44981ae3c5d92885ac089b2be825d2550e (diff)
downloadrtems-docs-0c978901d082c88a74f269ddf184438300c58213.tar.bz2
powerpc, sparc, sparc64: Correct tables
Diffstat (limited to 'cpu_supplement/sparc.rst')
-rw-r--r--cpu_supplement/sparc.rst55
1 files changed, 24 insertions, 31 deletions
diff --git a/cpu_supplement/sparc.rst b/cpu_supplement/sparc.rst
index 6b16bb6..f993cd8 100644
--- a/cpu_supplement/sparc.rst
+++ b/cpu_supplement/sparc.rst
@@ -236,34 +236,27 @@ architecturally defined role in the programming model which provides an
alternate name. The following table describes the mapping between the 32
registers and the register sets:
-+-----------------+----------------+------------------+
-| Register Number | Register Names | Description |
-+-----------------+----------------+------------------+
-| 0 - 7 | g0 - g7 | Global Registers |
-+-----------------+----------------+------------------+
-| 8 - 15 | o0 - o7 | Output Registers |
-+-----------------+----------------+------------------+
-| 16 - 23 | l0 - l7 | Local Registers |
-+-----------------+----------------+------------------+
-| 24 - 31 | i0 - i7 | Input Registers |
-+-----------------+----------------+------------------+
+================ ================ ===================
+Register Number Register Names Description
+================ ================ ===================
+0 - 7 g0 - g7 Global Registers
+8 - 15 o0 - o7 Output Registers
+16 - 23 l0 - l7 Local Registers
+24 - 31 i0 - i7 Input Registers
+================ ================ ===================
As mentioned above, some of the registers serve defined roles in the
programming model. The following table describes the role of each of these
registers:
-+---------------+----------------+----------------------+
-| Register Name | Alternate Name | Description |
-+---------------+----------------+----------------------+
-| g0 | na | reads return 0 |
-| | | writes are ignored |
-+---------------+----------------+----------------------+
-| o6 | sp | stack pointer |
-+---------------+----------------+----------------------+
-| i6 | fp | frame pointer |
-+---------------+----------------+----------------------+
-| i7 | na | return address |
-+---------------+----------------+----------------------+
+============== ================ ==================================
+Register Name Alternate Name Description
+============== ================ ==================================
+g0 na reads return 0, writes are ignored
+o6 sp stack pointer
+i6 fp frame pointer
+i7 na return address
+============== ================ ==================================
The registers g2 through g4 are reserved for applications. GCC uses them as
volatile registers by default. So they are treated like volatile registers in
@@ -483,14 +476,14 @@ endian fashion by the SPARC. Memory accesses which are not properly aligned
generate a "memory address not aligned" trap (type number 7). The following
table lists the alignment requirements for a variety of data accesses:
- +--------------+-----------------------+
- | Data Type | Alignment Requirement |
- +--------------+-----------------------+
- | byte | 1 |
- | half-word | 2 |
- | word | 4 |
- | doubleword | 8 |
- +--------------+-----------------------+
+============== ======================
+Data Type Alignment Requirement
+============== ======================
+byte 1
+half-word 2
+word 4
+doubleword 8
+============== ======================
Doubleword load and store operations must use a pair of registers as their
source or destination. This pair of registers must be an adjacent pair of