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| author | Joel Sherrill <joel@rtems.org> | 2016-10-28 13:07:04 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2016-10-28 13:10:22 -0500 |
| commit | 0c978901d082c88a74f269ddf184438300c58213 (patch) | |
| tree | 42919a9cc0036deb544dc7b0216f6920c72009cf /cpu_supplement/powerpc.rst | |
| parent | Remove the old files. (diff) | |
| download | rtems-docs-0c978901d082c88a74f269ddf184438300c58213.tar.bz2 | |
powerpc, sparc, sparc64: Correct tables
Diffstat (limited to 'cpu_supplement/powerpc.rst')
| -rw-r--r-- | cpu_supplement/powerpc.rst | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/cpu_supplement/powerpc.rst b/cpu_supplement/powerpc.rst index 5204ebc..3c5eb5c 100644 --- a/cpu_supplement/powerpc.rst +++ b/cpu_supplement/powerpc.rst @@ -373,14 +373,14 @@ architecture does not require the processor to generate alignment exceptions. The following table lists the alignment requirements for a variety of data accesses: -+--------------+-----------------------+ -| Data Type | Alignment Requirement | -+--------------+-----------------------+ -| byte | 1 | -| half-word | 2 | -| word | 4 | -| doubleword | 8 | -+--------------+-----------------------+ +============== ====================== +Data Type Alignment Requirement +============== ====================== +byte 1 +half-word 2 +word 4 +doubleword 8 +============== ====================== Doubleword load and store operations are only available in PowerPC CPU models which are sixty-four bit implementations. |