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author | Amar Takhar <amar@rtems.org> | 2016-01-16 20:13:02 -0500 |
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committer | Amar Takhar <verm@darkbeer.org> | 2016-05-02 20:51:23 -0400 |
commit | d755cbd36f5b4410994bcd468aee983471ab7167 (patch) | |
tree | 5992533991f9fe7332d264afd61700ee6836e7e2 /cpu_supplement/atmel_avr.rst | |
parent | Fix warnings. (diff) | |
download | rtems-docs-d755cbd36f5b4410994bcd468aee983471ab7167.tar.bz2 |
Split document into seperate files by section.
Diffstat (limited to 'cpu_supplement/atmel_avr.rst')
-rw-r--r-- | cpu_supplement/atmel_avr.rst | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/cpu_supplement/atmel_avr.rst b/cpu_supplement/atmel_avr.rst new file mode 100644 index 0000000..98743fb --- /dev/null +++ b/cpu_supplement/atmel_avr.rst @@ -0,0 +1,144 @@ +Atmel AVR Specific Information +############################## + +This chapter discusses the AVR architecture dependencies in this +port of RTEMS. + +**Architecture Documents** + +For information on the AVR architecture, refer to the following +documents available from Atmel. + +TBD + +- See other CPUs for documentation reference formatting examples. + +CPU Model Dependent Features +============================ + +CPUs of the AVR 53X only differ in the peripherals and thus in the +device drivers. This port does not yet support the 56X dual core variants. + +Count Leading Zeroes Instruction +-------------------------------- + +The AVR CPU has the XXX instruction which could be used to speed +up the find first bit operation. The use of this instruction should +significantly speed up the scheduling associated with a thread blocking. + +Calling Conventions +=================== + +Processor Background +-------------------- + +The AVR architecture supports a simple call and return mechanism. +A subroutine is invoked via the call (``call``) instruction. +This instruction saves the return address in the ``RETS`` register +and transfers the execution to the given address. + +It is the called funcions responsability to use the link instruction +to reserve space on the stack for the local variables. Returning from +a subroutine is done by using the RTS (``RTS``) instruction which +loads the PC with the adress stored in RETS. + +It is is important to note that the ``call`` instruction does not +automatically save or restore any registers. It is the responsibility +of the high-level language compiler to define the register preservation +and usage convention. + +Register Usage +-------------- + +A called function may clobber all registers, except RETS, R4-R7, P3-P5, +FP and SP. It may also modify the first 12 bytes in the callerâs stack +frame which is used as an argument area for the first three arguments +(which are passed in R0...R3 but may be placed on the stack by the +called function). + +Parameter Passing +----------------- + +RTEMS assumes that the AVR GCC calling convention is followed. +The first three parameters are stored in registers R0, R1, and R2. +All other parameters are put pushed on the stack. The result is returned +through register R0. + +Memory Model +============ + +The AVR family architecutre support a single unified 4 GB byte +address space using 32-bit addresses. It maps all resources like internal +and external memory and IO registers into separate sections of this +common address space. + +The AVR architcture supports some form of memory +protection via its Memory Management Unit. Since the +AVR port runs in supervisior mode this memory +protection mechanisms are not used. + +Interrupt Processing +==================== + +Discussed in this chapter are the AVR’s interrupt response and +control mechanisms as they pertain to RTEMS. + +Vectoring of an Interrupt Handler +--------------------------------- + +TBD + +Disabling of Interrupts by RTEMS +-------------------------------- + +During interrupt disable critical sections, RTEMS disables interrupts to +level N (N) before the execution of this section and restores them +to the previous level upon completion of the section. RTEMS uses the +instructions CLI and STI to enable and disable Interrupts. Emulation, +Reset, NMI and Exception Interrupts are never disabled. + +Interrupt Stack +--------------- + +The AVR Architecture works with two different kind of stacks, +User and Supervisor Stack. Since RTEMS and its Application run +in supervisor mode, all interrupts will use the interrupted +tasks stack for execution. + +Default Fatal Error Processing +============================== + +The default fatal error handler for the AVR performs the following +actions: + +- disables processor interrupts, + +- places the error code in *r0*, and + +- executes an infinite loop (``while(0);`` to + simulate a halt processor instruction. + +Symmetric Multiprocessing +========================= + +SMP is not supported. + +Thread-Local Storage +==================== + +Thread-local storage is not supported due to a broken tool chain. + +Board Support Packages +====================== + +System Reset +------------ + +TBD + +.. COMMENT: COPYRIGHT (c) 1988-2006. + +.. COMMENT: On-Line Applications Research Corporation (OAR). + +.. COMMENT: All rights reserved. + |