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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-11-10 10:16:03 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-11-10 10:16:30 +0100 |
| commit | 6297ad31d09bb5c0bddda418881296b7cbd20152 (patch) | |
| tree | 92be5b7024d84e0ba26afb77e49e2162509067c9 | |
| parent | waf: Users without the extra fonts need to use '--disable-extra-fonts' to bui... (diff) | |
| download | rtems-docs-6297ad31d09bb5c0bddda418881296b7cbd20152.tar.bz2 | |
cpu-supplement: Document PowerPC SPRG0-2 usage
| -rw-r--r-- | cpu-supplement/powerpc.rst | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/cpu-supplement/powerpc.rst b/cpu-supplement/powerpc.rst index b84c2b4..cd7847b 100644 --- a/cpu-supplement/powerpc.rst +++ b/cpu-supplement/powerpc.rst @@ -270,6 +270,17 @@ Special Registers The PowerPC architecture includes a number of special registers which are critical to the programming model: +*Special-Purpose Register General 0 (SPRG0)* + On SMP configurations, this register contains the address of the per-CPU + control of the processor. + +*Special-Purpose Register General 1 (SPRG1)* + This register contains the interrupt stack pointer for the outer-most + interrupt service routine. + +*Special-Purpose Register General 2 (SPRG2)* + This register contains the address of interrupt stack area begin. + *Machine State Register* The MSR contains the processor mode, power management mode, endian mode, exception information, privilege level, floating point available and |