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| author | Joel Sherrill <joel@rtems.org> | 2018-08-09 08:42:28 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2018-08-09 08:46:21 -0500 |
| commit | 99a84f904c9d85b1f50975765fec96123c542d32 (patch) | |
| tree | 53427d2a4bba1089e3212655506d29f42a3e70ca | |
| parent | RSB does not build a kernel by default. (diff) | |
| download | rtems-docs-99a84f904c9d85b1f50975765fec96123c542d32.tar.bz2 | |
Fix SPARC_SWTRAP_IRQDIS typo
close #3493.
| -rw-r--r-- | cpu-supplement/sparc.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu-supplement/sparc.rst b/cpu-supplement/sparc.rst index bb94435..c0924b8 100644 --- a/cpu-supplement/sparc.rst +++ b/cpu-supplement/sparc.rst @@ -658,7 +658,7 @@ as non-maskable interrupts. Interrupts are disabled or enabled by performing a system call to the Operating System reserved software traps 9 (SPARC_SWTRAP_IRQDIS) or 10 -(SPARC_SWTRAP_IRQDIS). The trap is generated by the software trap (Ticc) +(SPARC_SWTRAP_IRQEN). The trap is generated by the software trap (Ticc) instruction or indirectly by calling sparc_disable_interrupts() or sparc_enable_interrupts() functions. Disabling interrupts return the previous interrupt level (on trap entry) in register G1 and sets PSR.PIL to 15 to |