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.. SPDX-License-Identifier: CC-BY-SA-4.0
.. Copyright (C) 2014 Hesham Almatary
.. Copyright (C) 1989, 2007 On-Line Applications Research Corporation (OAR)
OpenRISC 1000 Specific Information
This chapter discusses the`OpenRISC 1000 architecture
http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There
are many implementations for OpenRISC like or1200 and mor1kx. Currently RTEMS
supports basic features that all implementations should have.
For information on the OpenRISC 1000 architecture refer to the`OpenRISC 1000
architecture manual http://openrisc.github.io/or1k.html.
Please refer to the`Function Calling Sequence
Floating Point Unit
A floating point unit is currently not supported.
A flat 32-bit memory model is supported.
OpenRISC 1000 architecture has 13 exception types:
- Bus Error
- Data Page Fault
- Instruction Page Fault
- Tick Timer
- Illegal Instruction
- External Interrupt
- D-TLB Miss
- I-TLB Miss
- System Call
- Floating Point
There are only two levels: interrupts enabled and interrupts disabled.
The OpenRISC RTEMS port uses a dedicated software interrupt stack. The stack
for interrupts is allocated during interrupt driver initialization. When an
interrupt is entered, the _ISR_Handler routine is responsible for switching
from the interrupted task stack to RTEMS software interrupt stack.
Default Fatal Error Processing
The default fatal error handler for this architecture performs the following
- disables operating system supported interrupts (IRQ),
- places the error code in ``r0``, and
- executes an infinite loop to simulate a halt processor instruction.
SMP is not supported.