From ec3417264d7be552593477bc8ac942fd6f187c89 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 2 May 2022 19:42:53 +0200 Subject: interface: Change register bits brief --- rtemsspec/interface.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'rtemsspec/interface.py') diff --git a/rtemsspec/interface.py b/rtemsspec/interface.py index 1f951b40..9df5576d 100644 --- a/rtemsspec/interface.py +++ b/rtemsspec/interface.py @@ -350,9 +350,10 @@ class Node: ctx.regs[name]["size"] = width // 8 ctx.regs[name]["type"] = f"uint{width}_t" ctx.regs[name]["group"] = group_ident - with self.content.defgroup_block(group_ident, name): + brief = self.substitute_text(register["brief"]) + with self.content.defgroup_block(group_ident, f"{brief} ({name})"): self.content.add_brief_description( - self.substitute_text(register["brief"])) + "This group contains register bit definitions.") self.content.doxyfy( self.substitute_text(register["description"])) self.content.add("@{") -- cgit v1.2.3