From ea3eadfc56e29cba361615ca61c15e0796c6a846 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 15 Mar 2023 08:39:35 +0100 Subject: interface: Improve register bit field macros Update #4828. --- rtemsspec/interface.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'rtemsspec/interface.py') diff --git a/rtemsspec/interface.py b/rtemsspec/interface.py index 525746cb..d14dff92 100644 --- a/rtemsspec/interface.py +++ b/rtemsspec/interface.py @@ -577,20 +577,21 @@ class Node: width = bit["width"] end = start + width sfx = "ULL" if end > 32 else "U" - define = f"#define {prefix.upper()}{bit['name'].upper()}" + base = f"{prefix.upper()}{bit['name'].upper()}" if index != 0: lines.append("") if width == 1: val = 1 << start - lines.append(f"{define} {val:#x}{sfx}") + lines.append(f"#define {base} {val:#x}{sfx}") else: mask = ((1 << width) - 1) << start - get = (1 << width) - 1 lines.extend([ - f"{define}_SHIFT {start}", f"{define}_MASK {mask:#x}{sfx}", - f"{define}_GET( _reg ) \\", - f" ( ( ( _reg ) >> {start} ) & {get:#x}{sfx} )", - f"{define}( _val ) ( ( _val ) << {start} )" + f"#define {base}_SHIFT {start}", + f"#define {base}_MASK {mask:#x}{sfx}", + f"#define {base}_GET( _reg ) \\", + f" ( ( ( _reg ) & {base}_MASK ) >> {base}_SHIFT )", + f"#define {base}( _val ) \\", + f" ( ( _val ) << {base}_SHIFT )" ]) return lines -- cgit v1.2.3