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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-01-11 10:33:55 +0100 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-01-11 10:34:52 +0100 |
commit | b66e5a24c44e8c6be1b91d231ae6c49e013dfe18 (patch) | |
tree | 597036a1575dba48b549b32466d6a0a6ba5df7f2 | |
parent | spec: Disable clock driver for intr tests (diff) | |
download | rtems-central-b66e5a24c44e8c6be1b91d231ae6c49e013dfe18.tar.bz2 |
spec: Improve some Interrupt Manager tests
Some interrupt controllers will signal a pending interrupt if it is
disabled (for example ARM GIC), others will not signal a pending
interrupt if it is disabled (for example Freescale/NXP MPIC).
-rw-r--r-- | spec/rtems/intr/req/is-pending.yml | 36 | ||||
-rw-r--r-- | spec/rtems/intr/req/raise-on.yml | 24 | ||||
-rw-r--r-- | spec/rtems/intr/req/raise.yml | 24 |
3 files changed, 46 insertions, 38 deletions
diff --git a/spec/rtems/intr/req/is-pending.yml b/spec/rtems/intr/req/is-pending.yml index 01ffcb56..2cfdc74f 100644 --- a/spec/rtems/intr/req/is-pending.yml +++ b/spec/rtems/intr/req/is-pending.yml @@ -285,8 +285,14 @@ test-support: | } else if ( !attr->is_maskable ) { /* We can only safely test maskable interrupts */ T_false( IsPending( ctx ) ); + } else if ( IsPending( ctx ) ) { + /* + * If there is already an interrupt pending, then it is probably raised + * by a peripheral which we cannot control. + */ } else if ( - attr->can_disable && ( attr->can_clear || attr->cleared_by_acknowledge ) + attr->can_raise && attr->can_disable && + ( attr->can_clear || attr->cleared_by_acknowledge ) ) { rtems_interrupt_entry entry; rtems_interrupt_level level; @@ -302,19 +308,21 @@ test-support: | T_rsc_success( sc ); if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) { - if ( attr->can_disable ) { - Disable( ctx ); - Raise( ctx ); - T_true( IsPending( ctx ) ); - - sc = rtems_interrupt_vector_enable( ctx->vector ); - T_rsc_success( sc ); - - while ( ctx->interrupt_count < 1 ) { - /* Wait */ - } - } else { - ++ctx->interrupt_count; + Disable( ctx ); + Raise( ctx ); + + /* + * Some interrupt controllers will signal a pending interrupt if it is + * disabled (for example ARM GIC), others will not signal a pending + * interrupt if it is disabled (for example Freescale/NXP MPIC). + */ + (void) IsPending( ctx ); + + sc = rtems_interrupt_vector_enable( ctx->vector ); + T_rsc_success( sc ); + + while ( ctx->interrupt_count < 1 ) { + /* Wait */ } rtems_interrupt_local_disable( level ); diff --git a/spec/rtems/intr/req/raise-on.yml b/spec/rtems/intr/req/raise-on.yml index 795d5e0f..6ce99467 100644 --- a/spec/rtems/intr/req/raise-on.yml +++ b/spec/rtems/intr/req/raise-on.yml @@ -343,21 +343,21 @@ test-support: | T_rsc_success( sc ); if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) { - T_false( IsPending( ctx ) ); + Disable( ctx ); + RaiseOn( ctx ); - if ( attr->can_disable ) { - Disable( ctx ); - RaiseOn( ctx ); - T_true( IsPending( ctx ) ); + /* + * Some interrupt controllers will signal a pending interrupt if it is + * disabled (for example ARM GIC), others will not signal a pending + * interrupt if it is disabled (for example Freescale/NXP MPIC). + */ + (void) IsPending( ctx ); - sc = rtems_interrupt_vector_enable( ctx->vector ); - T_rsc_success( sc ); + sc = rtems_interrupt_vector_enable( ctx->vector ); + T_rsc_success( sc ); - while ( ctx->interrupt_count < 1 ) { - /* Wait */ - } - } else { - ++ctx->interrupt_count; + while ( ctx->interrupt_count < 1 ) { + /* Wait */ } T_false( IsPending( ctx ) ); diff --git a/spec/rtems/intr/req/raise.yml b/spec/rtems/intr/req/raise.yml index 871a414e..3515b401 100644 --- a/spec/rtems/intr/req/raise.yml +++ b/spec/rtems/intr/req/raise.yml @@ -282,21 +282,21 @@ test-support: | T_rsc_success( sc ); if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) { - T_false( IsPending( ctx ) ); + Disable( ctx ); + Raise( ctx ); - if ( attr->can_disable ) { - Disable( ctx ); - Raise( ctx ); - T_true( IsPending( ctx ) ); + /* + * Some interrupt controllers will signal a pending interrupt if it is + * disabled (for example ARM GIC), others will not signal a pending + * interrupt if it is disabled (for example Freescale/NXP MPIC). + */ + (void) IsPending( ctx ); - sc = rtems_interrupt_vector_enable( ctx->vector ); - T_rsc_success( sc ); + sc = rtems_interrupt_vector_enable( ctx->vector ); + T_rsc_success( sc ); - while ( ctx->interrupt_count < 1 ) { - /* Wait */ - } - } else { - ++ctx->interrupt_count; + while ( ctx->interrupt_count < 1 ) { + /* Wait */ } T_false( IsPending( ctx ) ); |