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2020-04-10bsps/riscv: Fix multiple definitionSebastian Huber
2020-03-09imfs: Replace devfs with an IMFS specializationSebastian Huber
Add a simplified path evaluation function IMFS_eval_path_devfs() for a device only IMFS configuration. The code size can be further reduced by the application if it disables the support for legacy IO drivers via: #define CONFIGURE_IMFS_DISABLE_MKNOD #define CONFIGURE_IMFS_DISABLE_MKNOD_DEVICE Obsolete CONFIGURE_MAXIMUM_DEVICES. Remove BSP_MAXIMUM_DEVICES. Update #3894. Update #3898.
2020-02-04Use RTEMS_SYSINIT_ORDER_LAST_BUT_5Sebastian Huber
Use RTEMS_SYSINIT_ORDER_LAST_BUT_5 instead of RTEMS_SYSINIT_ORDER_LAST to allow applications and support functions to place system initialization handlers behind the standard handlers. Update #3838.
2020-02-04bsps: Add RamEnd to linker command filesSebastian Huber
Update #3838.
2019-11-29Regenerate headers.amSebastian Huber
2019-11-14bsp/riscv: Fix format and warningsSebastian Huber
Update #3785.
2019-11-14bsp/riscv: Fix use of uninitialized integerSebastian Huber
2019-11-14bsp/riscv: riscv_get_core_frequency()Sebastian Huber
Always provide this function. Return 0 by default. Fix formatting. Simplify function. Update #3785.
2019-10-30bsps/riscv: UART - Read reg-shift from DTB to properly set/get registersHesham Almatary
2019-10-27riscv: Add new BSP cfg variants to be built with llvm/clangHesham Almatary
2019-10-27riscv: Add new offending input sections to the linker scriptHesham Almatary
2019-10-27riscv: Add NOLOAD directive to the .work sectionHesham Almatary
ld.lld defaults .work to PROGBITS otherwise
2019-10-27riscv: Address differences in the linkerscript between GNU LD and LLVM/LLDHesham Almatary
LLVM/LLD does not support STARTUP and ALIGN_WITH_INPUT directives that GNU LD support. INPUT and ALIGN(8) are supported by LLVM/LLD and can replace the unsupported STARTUP/ALIGN_WITH_INPUT directives. The commit conditionally adds the supported directive that linkers can understand depending on the toolchain used to compile RTEMS i.e., clang or gcc. Clang is assumed to use LLD by default.
2019-10-27riscv: Generate linkcmds.base from the shared linkcmds.base.inHesham Almatary
This commit moves the existing linkcmds.base to linkcmds.base.in in order to make it configurable by autotools.
2019-10-23riscv: add freedom E310 Arty A7 bspPragnesh Patel
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2019-04-11score: Rename _SMP_Get_processor_count()Sebastian Huber
Rename _SMP_Get_processor_count() in _SMP_Get_processor_maximum() to be in line with the API level rtems_scheduler_get_processor_maximum(). Update #3732.
2019-04-09rtems: Add rtems_scheduler_get_processor_maximum()Sebastian Huber
Add rtems_scheduler_get_processor_maximum() as a replacement for rtems_get_processor_count(). The rtems_get_processor_count() is a bit orphaned. Adopt it by the Scheduler Manager. The count is also misleading, since the processor set may have gaps and the actual count of online processors may be less than the value returned by rtems_get_processor_count(). Update #3732.
2019-03-08bsps: Adjust shared Doxygen groupsSebastian Huber
Update #3706.
2019-03-08bsps: Adjust bsp.h Doxygen groupsSebastian Huber
Update #3706.
2019-03-04bsps: Adjust architecture Doxygen groupsSebastian Huber
- Use CamelCase as it is not used in our C code. Enables simple search and replace. - Prefix with "RTEMS" to aid deployment and integration. It aids searching and sorting. Update #3706.
2019-02-08griscv: add additional cpu configurationsJiri Gaisler
* Also switch default config to imafd as the C extension is not supported for code coverage
2019-01-22riscv: add griscv bspJiri Gaisler
Update #3678.
2019-01-08bsp/riscv: Clear boot command lineSebastian Huber
2018-11-08score: Rename interrupt stack symbolsSebastian Huber
Rename * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin, * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and * _Configuration_Interrupt_stack_size in _ISR_Stack_size. Move definitions to <rtems/score/isr.h>. The new names are considerable shorter and in the right namespace. Update #3459.
2018-09-17riscv: Allow platforms with no PLIC to proceedHesham Almatary
Spike simulator and QEMU's spike_v1.10 don't have a PLIC
2018-08-02bsp/riscv: Add missing BSP variantSebastian Huber
Update #3433.
2018-08-02bsp/riscv: Fix build with RTEMS_SMP undefinedSebastian Huber
Update #3433.
2018-08-02bsp/riscv: Fix a synchronization issue for PLICSebastian Huber
Update #3433.
2018-08-01bsp/riscv: Remove unused variableSebastian Huber
Update #3433.
2018-08-01bsp/riscv: Add NS16750 support to console driverSebastian Huber
Update #3433.
2018-08-01bsp/riscv: Initialize FPU depending on ISASebastian Huber
Initialize fcsr to zero for a defined rounding mode. Update #3433.
2018-08-01bsp/riscv: Fix clock driverSebastian Huber
Do not assume that mtime is zero at boot time. Update #3433.
2018-07-27bsp/riscv: Fix inter-processor interruptsSebastian Huber
The previous version worked only on a patched Qemu. Writes to mip are illegal according to the The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Privileged Architecture Version 1.10. Update #3433.
2018-07-27riscv: Rework CPU counter supportSebastian Huber
Update #3433.
2018-07-25bsp/riscv: Use interrupt driven NS16550 driverSebastian Huber
Update #3433.
2018-07-25bsp/riscv: Add PLIC supportSebastian Huber
Update #3433.
2018-07-25bsp/riscv: Add simple SMP support to clock driverSebastian Huber
This is a hack. The clock interrupt should be handled by each hart. Update #3433.
2018-07-25bsp/riscv: Use CPU counter btimerSebastian Huber
Update #3433.
2018-07-25bsp/riscv: Add basic SMP startupSebastian Huber
Update #3433.
2018-07-25riscv: Add CLINT and PLIC supportSebastian Huber
The CLINT and PLIC need some per-processor state. Update #3433.
2018-07-25bsps/riscv: Update linker-symbols.hSebastian Huber
Update #3433.
2018-07-25bsp/riscv: Add reset via for SiFive Test FinisherSebastian Huber
Update #3433.
2018-07-25bsp/riscv: Add and use riscv_fdt_get_address()Sebastian Huber
Update #3433.
2018-07-25bsp/riscv: Fix HTIF warningsSebastian Huber
Update #3433.
2018-07-25riscv: Rework exception handlingSebastian Huber
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
2018-07-06bsp/riscv: Add console support for NS16550 devicesSebastian Huber
Update #3433.
2018-07-06bsp/riscv: Simplify printk() supportSebastian Huber
This is a prepartion to add NS16550 driver support to the console driver. Update #3433.
2018-07-06riscv: Add LADDR assembler defineSebastian Huber
An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
2018-07-06riscv: Implement CPU counterSebastian Huber
Update #3433.
2018-07-05bsps: Update headers.amSebastian Huber
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