/dts-v1/;

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	compatible = "riscv-virtio";
	model = "riscv-virtio,qemu";

	chosen {
		bootargs = [00];
		stdout-path = "/soc/uart@10000000";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		timebase-frequency = <0x2FAF080>;

		cpu@0 {
			phandle = <0x7>;
			device_type = "cpu";
			reg = <0x0>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv32imafdcsu";
			mmu-type = "riscv,sv32";

			interrupt-controller {
				#interrupt-cells = <0x1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x8>;
			};
		};

		cpu@1 {
			phandle = <0x5>;
			device_type = "cpu";
			reg = <0x1>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv32imafdcsu";
			mmu-type = "riscv,sv32";

			interrupt-controller {
				#interrupt-cells = <0x1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x6>;
			};
		};

		cpu@2 {
			phandle = <0x3>;
			device_type = "cpu";
			reg = <0x2>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv32imafdcsu";
			mmu-type = "riscv,sv32";

			interrupt-controller {
				#interrupt-cells = <0x1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x4>;
			};
		};

		cpu@3 {
			phandle = <0x1>;
			device_type = "cpu";
			reg = <0x3>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv32imafdcsu";
			mmu-type = "riscv,sv32";

			interrupt-controller {
				#interrupt-cells = <0x1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x2>;
			};
		};

		cpu-map {

			cluster0 {

				core0 {
					cpu = <0x7>;
				};

				core1 {
					cpu = <0x5>;
				};

				core2 {
					cpu = <0x3>;
				};

				core3 {
					cpu = <0x1>;
				};
			};
		};
	};

	soc {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		compatible = "simple-bus";
		ranges;

		flash@20000000 {
			bank-width = <0x4>;
			reg = <0x0 0x20000000 0x0 0x2000000 0x0 0x22000000 0x0 0x2000000>;
			compatible = "cfi-flash";
		};

		rtc@101000 {
			interrupts = <0xb>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x101000 0x0 0x1000>;
			compatible = "google,goldfish-rtc";
		};

		uart@10000000 {
			interrupts = <0xa>;
			interrupt-parent = <0x9>;
			clock-frequency = <0x384000>;
			reg-shift = <0x2>;
			reg = <0x0 0x10000000 0x0 0x100>;
			compatible = "ns16550a";
		};

		poweroff {
			value = <0x5555>;
			offset = <0x0>;
			regmap = <0xa>;
			compatible = "syscon-poweroff";
		};

		reboot {
			value = <0x7777>;
			offset = <0x0>;
			regmap = <0xa>;
			compatible = "syscon-reboot";
		};

		test@100000 {
			phandle = <0xa>;
			reg = <0x0 0x100000 0x0 0x1000>;
			compatible = "sifive,test1", "sifive,test0", "syscon";
		};

		pci@30000000 {
			interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x9 0x20 0x0 0x0 0x0 0x2 0x9 0x21 0x0 0x0 0x0 0x3 0x9 0x22 0x0 0x0 0x0 0x4 0x9 0x23 0x800 0x0 0x0 0x1 0x9 0x21 0x800 0x0 0x0 0x2 0x9 0x22 0x800 0x0 0x0 0x3 0x9 0x23 0x800 0x0 0x0 0x4 0x9 0x20 0x1000 0x0 0x0 0x1 0x9 0x22 0x1000 0x0 0x0 0x2 0x9 0x23 0x1000 0x0 0x0 0x3 0x9 0x20 0x1000 0x0 0x0 0x4 0x9 0x21 0x1800 0x0 0x0 0x1 0x9 0x23 0x1800 0x0 0x0 0x2 0x9 0x20 0x1800 0x0 0x0 0x3 0x9 0x21 0x1800 0x0 0x0 0x4 0x9 0x22>;
			ranges = <0x1000000 0x0 0x0 0x0 0x3000000 0x0 0x10000 0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
			reg = <0x0 0x30000000 0x0 0x10000000>;
			dma-coherent;
			bus-range = <0x0 0xff>;
			linux,pci-domain = <0x0>;
			device_type = "pci";
			compatible = "pci-host-ecam-generic";
			#size-cells = <0x2>;
			#interrupt-cells = <0x1>;
			#address-cells = <0x3>;
		};

		virtio_mmio@10008000 {
			interrupts = <0x8>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10008000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		virtio_mmio@10007000 {
			interrupts = <0x7>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10007000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		virtio_mmio@10006000 {
			interrupts = <0x6>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10006000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		virtio_mmio@10005000 {
			interrupts = <0x5>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10005000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		virtio_mmio@10004000 {
			interrupts = <0x4>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10004000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		virtio_mmio@10003000 {
			interrupts = <0x3>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10003000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		virtio_mmio@10002000 {
			interrupts = <0x2>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10002000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		virtio_mmio@10001000 {
			interrupts = <0x1>;
			interrupt-parent = <0x9>;
			reg = <0x0 0x10001000 0x0 0x1000>;
			compatible = "virtio,mmio";
		};

		plic@c000000 {
			phandle = <0x9>;
			riscv,ndev = <0x35>;
			reg = <0x0 0xc000000 0x0 0x210000>;
			interrupts-extended = <0x8 0xb 0x8 0x9 0x6 0xb 0x6 0x9 0x4 0xb 0x4 0x9 0x2 0xb 0x2 0x9>;
			interrupt-controller;
			compatible = "riscv,plic0";
			#interrupt-cells = <0x1>;
			#address-cells = <0x0>;
		};

		clint@2000000 {
			interrupts-extended = <0x8 0x3 0x8 0x7 0x6 0x3 0x6 0x7 0x4 0x3 0x4 0x7 0x2 0x3 0x2 0x7>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			compatible = "riscv,clint0";
		};
	};
};