| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-10-26 | Bumped version to 2.30 | Jiri Gaisler |
| 2021-08-04 | Support extended interrupts2.29 | Sebastian Huber |
| 2021-07-30 | Added GR740 L2 configuration register2.28 | Jiri Gaisler |
| 2020-12-15 | Added support for RISCV32 systems with CLINT/PLIC | Jiri Gaisler |
| 2020-12-01 | Added emulation of GR740 SOC2.25 | Jiri Gaisler |
| 2020-10-28 | Add networking support using host tap device2.23 | Jiri Gaisler |
| 2020-09-09 | Map RISC-V FPU CSR on host cpu using fenv.h | Jiri Gaisler |
| 2020-02-29 | Update to version 2.212.21 | Jiri Gaisler |
| 2019-11-09 | Support building on MinGW-W64/MSYS22.19 | Jiri Gaisler |
| 2019-07-02 | Make readline conditional and add linenoise it not present. | Chris Johns |
| 2019-05-28 | Made L1 cache optional through --enable-l1cache | Jiri Gaisler |
| 2019-05-14 | Standalone sis - initial commit | Jiri Gaisler |
 |
index : sis.git | |
| Clone of master repository. |
| summaryrefslogtreecommitdiff |