diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-03-15 21:34:56 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-03-15 21:34:56 +0000 |
| commit | 23005aab5a185f41283c8d6b54a2d042829ad8e0 (patch) | |
| tree | fd6047f0586039bf2e16432349da7530391eb199 /c | |
| parent | f6c010a7c209312bd8da21821b53365a6c8fec0c (diff) | |
2011-03-15 Till Straumann <strauman@slac.stanford.edu>
* startup/bspstart.c: Fix clock code on qemu. Also ensure UART is
initialized early for printk.
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/m68k/uC5282/ChangeLog | 5 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c | 25 |
2 files changed, 25 insertions, 5 deletions
diff --git a/c/src/lib/libbsp/m68k/uC5282/ChangeLog b/c/src/lib/libbsp/m68k/uC5282/ChangeLog index f42047c577..e11057c174 100644 --- a/c/src/lib/libbsp/m68k/uC5282/ChangeLog +++ b/c/src/lib/libbsp/m68k/uC5282/ChangeLog @@ -1,3 +1,8 @@ +2011-03-15 Till Straumann <strauman@slac.stanford.edu> + + * startup/bspstart.c: Fix clock code on qemu. Also ensure UART is + initialized early for printk. + 2011-03-04 Till Straumann <strauman@slac.stanford.edu> PR 1738/bsps diff --git a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c index 53c7f7a665..2502b5d2c1 100644 --- a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @@ -244,6 +244,14 @@ void bsp_start( void ) int i; const char *clk_speed_str; uint32_t clk_speed, mfd, rfd; + uint8_t byte; + + /* + * Make sure UART TX is running - necessary for + * early printk to work. The firmware monitor + * usually enables this anyways but qemu doesn't! + */ + MCF5282_UART_UCR(CONSOLE_PORT) = MCF5282_UART_UCR_TX_ENABLED; /* * Set up default exception handler @@ -334,12 +342,19 @@ void bsp_start( void ) if ( 0 == clk_speed ) { printk("Using some heuristics to determine clock speed...\n"); - printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock); - if ( 0xf8 != MCF5282_CLOCK_SYNSR ) { - printk("FATAL ERROR: Unexpected SYNSR contents, can't proceed\n"); - bsp_sysReset(0); + byte = MCF5282_CLOCK_SYNSR; + if ( 0 == byte ) { + printk("SYNSR == 0; assuming QEMU at 66MHz\n"); + BSP_pll_ref_clock = 8250000; + mfd = ( 0 << 8 ) | ( 2 << 12 ); + } else { + if ( 0xf8 != byte ) { + printk("FATAL ERROR: Unexpected SYNSR contents (0x%02x), can't proceed\n", byte); + bsp_sysReset(0); + } + mfd = MCF5282_CLOCK_SYNCR; } - mfd = MCF5282_CLOCK_SYNCR; + printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock); rfd = (mfd >> 8) & 7; mfd = (mfd >> 12) & 7; /* Check against 'known' cases */ |