diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2009-05-04 20:06:43 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2009-05-04 20:06:43 +0000 |
| commit | d7196bfd6696be61880fff7db8ca4de044c30748 (patch) | |
| tree | 8c4a921d1cadc7dfec6bb91d1613fd8461f3528a | |
| parent | e1be2b30ad3b43c28cba087614a6ebca6356445e (diff) | |
2009-04-20 Kate Feng <feng1@bnl.gov>
1396/bsps
* pci/pci.c : Updated it to be consistent with the original pci.c
* written by Eric Valette. There is no change in its function.
* irq/irq_init.c : set defaultIrq->next_handler to be 0
* for BSP_SHARED_HANDLER_SUPPORT.
* network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver.
* irq/BSP_irq.c : added supports for shared IRQ.
* pci/pci_interface.c : Enabled PCI "Read", "Read Line", and
"Read Multiple"
* Agressive Prefetch to improve the performance of the PCI based
* applications (e.g. 1GHz NIC).
* irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
* register to monitor the cause of the level sensitive interrupts.
* This unique solution solves various bugs in the 1GHz network drivers
* Fixed bugs in compute_pic_masks_from_prio()
30 files changed, 1127 insertions, 906 deletions
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog b/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog index 3df6fa2bc7..bd7c0bd1a8 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog +++ b/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog @@ -1,3 +1,39 @@ +2009-04-20 Kate Feng <feng1@bnl.gov> + + 1396/bsps + * pci/pci.c : Updated it to be consistent with the original pci.c + * written by Eric Valette. There is no change in its function. + * irq/irq_init.c : set defaultIrq->next_handler to be 0 + * for BSP_SHARED_HANDLER_SUPPORT. + * network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver. + * irq/BSP_irq.c : added supports for shared IRQ. + * pci/pci_interface.c : Enabled PCI "Read", "Read Line", and + "Read Multiple" + * Agressive Prefetch to improve the performance of the PCI based + * applications (e.g. 1GHz NIC). + * irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value + * register to monitor the cause of the level sensitive interrupts. + * This unique solution solves various bugs in the 1GHz network drivers + * Fixed bugs in compute_pic_masks_from_prio() + +2009-04-20 Kate Feng <feng1@bnl.gov> + + 1396/bsps + * pci/pci.c : Updated it to be consistent with the original pci.c + * written by Eric Valette. There is no change in its function. + * irq/irq_init.c : set defaultIrq->next_handler to be 0 + * for BSP_SHARED_HANDLER_SUPPORT. + * network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver. + * irq/BSP_irq.c : added supports for shared IRQ. + * pci/pci_interface.c : Enabled PCI "Read", "Read Line", and + "Read Multiple" + * Agressive Prefetch to improve the performance of the PCI based + * applications (e.g. 1GHz NIC). + * irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value + * register to monitor the cause of the level sensitive interrupts. + * This unique solution solves various bugs in the 1GHz network drivers + * Fixed bugs in compute_pic_masks_from_prio() + 2007-11-30 Joel Sherrill <joel.sherrill@OARcorp.com> * irq/GT64260Int.c, network/if_100MHz/Makefile.am, @@ -6,7 +42,7 @@ 2007-09-20 Kate Feng <feng1@bnl.gov> * network/if_100MHz/GT64260eth.c: Add else. - + 2007-09-19 Kate Feng <feng1@bnl.gov> * README: Update. diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c index 27691e8d81..a049a887c3 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c @@ -1,7 +1,8 @@ /* GT64260TWSI.c : Two-Wire Serial Interface (TWSI) support for the GT64260 * - * Copyright (c) 2004, Brookhaven National Laboratory and - * Shuchen Kate Feng <feng1@bnl.gov> + * Copyright (c) 2004, Brookhaven National Laboratory + * and Shuchen Kate Feng <feng1@bnl.gov> + * under the Deaprtment of Energy contract DE-AC02-98CH10886 * All rights reserved. * * The license and distribution terms for this file may be diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h index 1027c26b7f..52e4dfe18a 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h @@ -1,5 +1,9 @@ /* * $Id$ + * + * Copyright 2003 S. Kate Feng <feng1@bnl.gov>, + * NSLS, Brookhaven National Laboratory. All rights reserved. + * under the Deaprtment of Energy contract DE-AC02-98CH10886 */ #ifndef __GT64260TWSI_h diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c index ff64924485..cd82953644 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c @@ -2,6 +2,7 @@ * * Copyright (c) 2003, 2004 Brookhaven National Laboratory * Author: S. Kate Feng <feng1@bnl.gov> + * under the Deaprtment of Energy contract DE-AC02-98CH10886 * All rights reserved. * * The license and distribution terms for this file may be @@ -29,9 +30,10 @@ unchar I2cDevByteAddr(u32 devA2A1A0, unchar byteNum) /**************************************************************************** * I2Cread_eeprom - read EEPROM VPD from the I2C */ -int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,unchar *pBuff,u32 numBytes) +int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,void *pBuff,u32 numBytes) { int status=0, lastByte=0; + unchar *ptr=(unchar *) pBuff; switch (AddrBytes) { case 1: @@ -83,12 +85,15 @@ int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,unchar *pBuff,u /* read data from device */ for ( ; numBytes > 0; numBytes-- ) { if ( numBytes == 1) lastByte=1; - if (GT64260TWSIread(pBuff,lastByte) == -1) return (-1); + if (GT64260TWSIread(ptr,lastByte) == -1) { + printk("numBytes %d\n", numBytes); + return (-1); + } #ifdef I2C_DEBUG - printk("%2x ", *pBuff); + printk("%2x ", *ptr); if ( (numBytes % 20)==0 ) printk("\n"); #endif - pBuff++; + ptr++; } #ifdef I2C_DEBUG printk("\n"); diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h index 4b37de6927..7dedb4390e 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h @@ -2,10 +2,74 @@ * * (C) 2004, NSLS, Brookhaven National Laboratory, * S. Kate Feng, <feng1@bnl.gov> - * + * under the Deaprtment of Energy contract DE-AC02-98CH10886 */ extern unsigned char ConfVPD_buff[200]; -#define VPD_ENET0_OFFSET 0x3c -#define VPD_ENET1_OFFSET 0x45 +typedef struct ConfVpdRec { + char VendorId[8]; + char pad0[4]; + char BrdId[13]; + char pad1[2]; + char ManAssmNum[12]; + char pad2[2]; + char SerialNum[7]; + char pad3[2]; + /* char IntClk[4];*/ + uint32_t IntClk; + char pad4[3]; + /*char ExtClk[4];*/ + uint32_t ExtClk; + char pad5[3]; + char EnetAddr0[7]; + char pad6[2]; + char EnetAddr1[7]; + char pad7[20]; +} ConfVpdRec_t; + +#define VPD_BOARD_ID 8 +#define VPD_ENET0_OFFSET 0x40 +#define VPD_ENET1_OFFSET 0x49 + +/* +4D4F544F 524F4C41 0200010D 4D564D45 MOTOROLA....MVME +35353030 2D303136 33020C30 312D5733 5500-0163..01-W3 +38323946 30314403 07373035 31383238 829F01D..7051828 +05053B9A CA000106 0507F281 55010807 ..;.........U... +ethernet address +xxxxxxxx xxxxxxxx xxxxxxxx xxxx3701 ................ +09043734 35350A04 87A6E98C 0B0C0089 ..7455..."=..... +00181002 02101000 78070B0C FFFFFFFF ........x....... +10020210 10017805 0E0FFFFF FFFFFFFF ......x......... +FFFFFF01 FF01FFFF FF0F0400 03000019 ................ +0A010107 02030000 000100FF FFFFFFFF ................ +FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................ +FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................ +00000000 00000000 00000000 00000000 ................ +00000000 00000000 00000000 00000000 ................ +00000000 00000000 00000000 00000000 ................ +00000000 00000000 00000000 00000000 ................ + +For the MVME5500 : + +Product Identifier : MVME5500-0163 +Manufacturing Assembly Number : 01-W3829F01D +Serial Number : 7051828 +Internal Clock Speed (Hertz) : 3B9ACA00 (&1000000000) +External Clock Speed (Hertz) : 07F28155 (&133333333) +Ethernet Address : xx xx xx xx xx xx xx +Ethernet Address : xx xx xx xx xx xx xx +Microprocessor Type : 7455 +SROM/EEPROM CRC : D3223DD0 (&-752730672) +Flash0 Memory Configuration : 00 89 00 18 10 02 02 10 + : 10 00 78 07 +Flash1 Memory Configuration : FF FF FF FF 10 02 02 10 + : 10 01 78 05 +L2 Cache Configuration : FF FF FF FF FF FF FF FF + : FF 01 FF 01 FF FF FF +VPD Revision : 00 03 00 00 +L3 Cache Configuration : 01 01 07 02 03 00 00 00 + : 01 00 + +*/ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h index b58b086565..edbea4e2b5 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h @@ -190,7 +190,7 @@ #define GT_MPP_Control2 0xf008 #define GT_MPP_Control3 0xf00c -/* <skf> added */ +/* <skf> added for GT64260 */ #define GT_MPP_SerialPortMultiplex 0xf010 #define GT_GPP_IO_Control 0xf100 @@ -790,13 +790,25 @@ #define TWSI_SFT_RST 0xc01c /* Interrupt Controller - Interrupt Controller Registers */ +/* <skf> added for GT64360 */ + +#define GT64360_MAIN_INT_CAUSE_LO 0x004 /* read Only */ +#define GT64360_MAIN_INT_CAUSE_HI 0x00c /* read Only */ +#define GT64360_CPU0_INT_MASK_LO 0x014 +#define GT64360_CPU0_INT_MASK_HI 0x01c +#define GT64360_CPU0_SEL_CAUSE 0x024 /* read Only */ + +#define GT64360_CPU1_INT_MASK_LO 0x034 +#define GT64360_CPU1_INT_MASK_HI 0x03c +#define GT64360_CPU1_SEL_CAUSE 0x044 /* read Only */ + /* Section 25.2 : Table 734 <skf> */ -#define GT_MAIN_INT_CAUSE_LO 0xc18 /* read Only */ -#define GT_MAIN_INT_CAUSE_HI 0xc68 /* read Only */ -#define GT_CPU_INT_MASK_LO 0xc1c -#define GT_CPU_INT_MASK_HI 0xc6c -#define GT_CPU_SEL_CAUSE 0xc70 /* read Only */ +#define GT64260_MAIN_INT_CAUSE_LO 0xc18 /* read Only */ +#define GT64260_MAIN_INT_CAUSE_HI 0xc68 /* read Only */ +#define GT64260_CPU_INT_MASK_LO 0xc1c +#define GT64260_CPU_INT_MASK_HI 0xc6c +#define GT64260_CPU_SEL_CAUSE 0xc70 /* read Only */ #define GT_PCI0_INT_MASK_LO 0xc24 #define GT_PCI0_INT_MASK_HI 0xc64 #define GT_PCI0_SEL_CAUSE 0xc74 /* read Only */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am b/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am index 169c20862d..9c1ec49f7a 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am +++ b/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am @@ -35,7 +35,8 @@ startup_rel_SOURCES = startup/bspstart.c \ ../../powerpc/shared/startup/pretaskinghook.c \ ../../powerpc/shared/startup/sbrk.c ../../shared/bootcard.c \ startup/bspclean.c ../../shared/bsplibc.c ../../shared/bsppost.c \ - ../../shared/gnatinstallhandler.c startup/reboot.c + ../../shared/gnatinstallhandler.c startup/reboot.c \ + ../../powerpc/shared/startup/probeMemEnd.c startup_rel_CPPFLAGS = $(AM_CPPFLAGS) startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) @@ -68,8 +69,8 @@ pci_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) include_bsp_HEADERS += irq/irq.h noinst_PROGRAMS += irq.rel -irq_rel_SOURCES = irq/irq_init.c irq/irq.c \ - ../../powerpc/shared/irq/irq_asm.S +irq_rel_SOURCES = irq/irq_init.c irq/BSP_irq.c \ + ../../powerpc/shared/irq/irq.c ../../powerpc/shared/irq/irq_asm.S irq_rel_CPPFLAGS = $(AM_CPPFLAGS) irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) @@ -108,8 +109,9 @@ include_bsp_HEADERS += network/if_100MHz/GT64260eth.h \ network_CPPFLAGS = -D_KERNEL noinst_PROGRAMS += network.rel -network_rel_SOURCES = network/if_100MHz/GT64260eth.c \ - network/if_1GHz/if_wm.c network/if_1GHz/pci_map.c +network_rel_SOURCES = network/if_100MHz/GT64260eth.c network/if_1GHz/if_wm.c \ + network/if_1GHz/pci_map.c + network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS) network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif @@ -123,8 +125,8 @@ include_bsp_HEADERS += ../../shared/vmeUniverse/VME.h vme/VMEConfig.h \ noinst_PROGRAMS += vme.rel vme_rel_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c\ - ../shared/vme/vmeconfig.c ../../shared/vmeUniverse/bspVmeDmaList.c\ - ../shared/vme/vme_universe.c ../shared/vme/vme_universe_dma.c + vme/vmeconfig.c ../../shared/vmeUniverse/bspVmeDmaList.c\ + ../shared/vme/vme_universe_dma.c vme_rel_CPPFLAGS = $(AM_CPPFLAGS) vme_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) diff --git a/c/src/lib/libbsp/powerpc/mvme5500/README b/c/src/lib/libbsp/powerpc/mvme5500/README index 53986d4bac..0896066c9c 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/README +++ b/c/src/lib/libbsp/powerpc/mvme5500/README @@ -1,5 +1,5 @@ # -# $Id: README,v 1.3.1 Shuchen Kate Feng, NSLS, BNL (08/27/07) +# $Id: README,v 1.4.1 Shuchen Kate Feng, NSLS, BNL (03/16/2009) # Please reference README.booting for the boot/load process. @@ -7,7 +7,7 @@ Please reference README.booting for the boot/load process. For the priority setting of the Interrupt Requests (IRQs), please reference README.irq -The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release. +The BSP is built and tested on the 4.8.0 RTEMS release. I believe in valuable real-time programming, where technical neatness, performance and truth are. I hope I still believe. Any suggestion, diff --git a/c/src/lib/libbsp/powerpc/mvme5500/README.booting b/c/src/lib/libbsp/powerpc/mvme5500/README.booting index 19e9567908..0c4c8c3e9c 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/README.booting +++ b/c/src/lib/libbsp/powerpc/mvme5500/README.booting @@ -1,8 +1,6 @@ -README.booting: written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 2007 +README.booting: written by S. Kate Feng <feng1@bnl.gov>, March 16, 2009 -The bootloader is adapted from Till Straumann's Generic Mini-loader, -which he wrote originally for the SVGM powerpc board. -The BSP is built and tested on the 4.7 CVS RTEMS release. +The BSP is built and tested on the RTEMS 4.8.0 release. Booting requirement : ------------------------- @@ -11,12 +9,7 @@ Booting requirement : or /etc/dhcpd.conf (DHCP) properly to boot the system. (Note : EPICS needs a NTP server). -2) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin) - and perhaps others (e.g. misc/st.sys) to the /tftpboot/epics/hostname/bin/ - directory or the TFTPBOOT one you specified in the 'tftpGet' - command of the boot script (as shown in the following example). - -3) Example of the boot script setup carried out on the MOTLoad +2) Example of the boot script setup carried out on the MOTLoad command line : MVME5500> gevEdit mot-script-boot @@ -32,23 +25,14 @@ MVME5500> Note : (cxx.xx.xx.xx is the client IP address and sxx.xx.xx.xx is the server IP address) -4) Other reference web sites for mvme5500 BSP: -http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt +3) Other reference web sites for mvme5500 BSP: http://www.nsls.bnl.gov/facility/expsys/software/EPICS/ -http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt -5) When generating code (especially C++) for this system, one should - use at least gcc-3.2 (preferrably a copy downloaded from the RTEMS - site [snapshot area] ) -6) To reboot the RTEMS-MVME5500 (board reset), one can invoke the +4) To reboot the RTEMS-MVME5500 (board reset), one can invoke the rtemsReboot() command at Cexp> prompt. -7) Please reference http://www.slac.stanford.edu/~strauman/rtems -for the source code and installation guidance of cexp, GeSys and -other useful utilities such as telnet, nfs, and so on. - -8) To get started with RTEMS/EPICS and to build development +5) To get started with RTEMS/EPICS and to build development tools and BSP, I would recommend one to reference http://www.aps.anl.gov/epics/base/RTEMS/tutorial/ in additional to the RTEMS document. diff --git a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h index 043536ead7..8d53f99a73 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h @@ -7,7 +7,8 @@ * found in found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. + * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. + * * */ @@ -22,10 +23,57 @@ #include <libcpu/io.h> #include <bsp/vectors.h> -#include <bsp/bspMvme5500.h> +/* Board type */ +typedef enum { + undefined = 0, + MVME5500, + MVME6100 +} BSP_BoardTypes; + +BSP_BoardTypes BSP_getBoardType(); + +/* Board type */ +typedef enum { + Undefined, + UNIVERSE2, + TSI148, +} BSP_VMEchipTypes; + +BSP_VMEchipTypes BSP_getVMEchipType(); + +/* The version of Discovery system controller */ + +typedef enum { + notdefined, + GT64260A, + GT64260B, + MV64360, +} DiscoveryChipVersion; + +DiscoveryChipVersion BSP_getDiscoveryChipVersion(); + +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ +#define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ + +#define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base + */ +#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ -#define _IO_BASE GT64260_REG_BASE +#define _IO_BASE GT64x60_REG_BASE + +#define BSP_NVRAM_BASE_ADDR 0xf1110000 + +#define BSP_RTC_INTA_REG 0x7ff0 +#define BSP_RTC_SECOND 0x7ff2 +#define BSP_RTC_MINUTE 0x7ff3 +#define BSP_RTC_HOUR 0x7ff4 +#define BSP_RTC_DATE 0x7ff5 +#define BSP_RTC_INTERRUPTS 0x7ff6 +#define BSP_RTC_WATCHDOG 0x7ff7 /* PCI0 Domain I/O space */ #define PCI0_IO_BASE 0xf0000000 @@ -72,16 +120,13 @@ #define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) /* uart.c uses out_8 instead of outb */ -#define BSP_UART_IOBASE_COM1 GT64260_DEV1_BASE + 0x20000 -#define BSP_UART_IOBASE_COM2 GT64260_DEV1_BASE + 0x21000 +#define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 +#define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ #define BSP_UART_BAUD_BASE 115200 /* - * Vital Board data Start using DATA RESIDUAL - */ -/* * Total memory using RESIDUAL DATA */ extern unsigned int BSP_mem_size; @@ -120,19 +165,26 @@ extern unsigned int BSP_heap_start; #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach #endif -extern int -RTEMS_BSP_NETWORK_DRIVER_ATTACH(/* struct rtems_bsdnet_ifconfig * */); +extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(); + +#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER() -/* As per Linux, This should be in the ppc/system.h */ +static inline void lwmemBar() +{ + asm volatile("lwsync":::"memory"); +} +static inline void io_flush() +{ + asm volatile("isync":::"memory"); +} static inline void memBar() { asm volatile("sync":::"memory"); } - static inline void ioBar() { - asm volatile("eieio"); + asm volatile("eieio":::"memory"); } #endif diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c b/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c index a4a82448f4..00ac8eb952 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c @@ -1,4 +1,4 @@ -/* irq.c +/* BSP_irq.c * * This file contains the implementation of the function described in irq.h * @@ -8,21 +8,25 @@ * found in the file LICENSE in this distribution or at * http://www.OARcorp.com/rtems/license.html. * - * Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu> - * for some inputs. + * Acknowledgement to Till Straumann <strauman@slac.stanford.edu> + * for some inputs in May 2004. * * Copyright 2003, 2004, 2005, 2007 Shuchen Kate Feng <feng1@bnl.gov>, - * NSLS,Brookhaven National Laboratory - * 1) Modified and added support for the MVME5500 board. - * 2) The implementation of picIsrTable[] is an original work by the + * NSLS, Brookhaven National Laboratory. All rights reserved. + * + * 1) Used GT_GPP_Value register instead of the GT_GPP_Interrupt_Cause + * register to monitor the cause of the level sensitive interrupts. + * (Copyright : NDA item) + * 2) The implementation of picPrioTable[] is an original work by the * author to optimize the software IRQ priority scheduling because * Discovery controller does not provide H/W IRQ priority schedule. * It ensures the fastest/faster interrupt service to the * highest/higher priority IRQ, if pendig. * 3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER() - * + * */ - + +#include <stdio.h> #include <rtems/system.h> #include <bsp.h> #include <bsp/irq.h> @@ -39,9 +43,7 @@ #define HI_INT_CAUSE 0x40000000 -#define MAX_IRQ_LOOP 30 - -#define EDGE_TRIGGER +#define MAX_IRQ_LOOP 20 #define _MSR_GET( _mask) \ do { \ @@ -76,41 +78,42 @@ static rtems_irq_connect_data default_rtems_entry; /* * location used to store initial tables used for interrupt - * management. + * management.BSP copy of the configuration */ -static rtems_irq_global_settings* internal_config; -static rtems_irq_connect_data* rtems_hdl_tbl; +static rtems_irq_global_settings BSP_config; static volatile unsigned *BSP_irqMask_reg[3]; static volatile unsigned *BSP_irqCause_reg[3]; static volatile unsigned BSP_irqMask_cache[3]={0,0,0}; +static unsigned int BSP_GPP_mask[4]= { 1<<24, 1<<25, 1<<26, 1<<27}; - -static int picIsrTblPtr=0; +static int picPrioTblPtr=0; static unsigned int GPPIrqInTbl=0; static unsigned long long MainIrqInTbl=0; /* - * The software developers are forbidden to setup picIsrTable[], + * The software developers are forbidden to setup picPrioTable[], * as it is a powerful engine for the BSP to find the pending * highest priority IRQ at run time. It ensures the fastest/faster * interrupt service to the highest/higher priority IRQ, if pendig. * - * The picIsrTable[96] is updated dynamically at run time + * The picPrioTable[96] is updated dynamically at run time * based on the priority levels set at BSPirqPrioTable[96], - * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq() + * while the BSP_enable_irq_at_pic(), and BSP_disable_irq_at_pic() * commands are invoked. * - * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt + * The picPrioTable[96] lists the enabled CPU main and GPP external interrupt * numbers [0 (lowest)- 95 (highest)] starting from the highest priority * one to the lowest priority one. The highest priority interrupt is - * located at picIsrTable[0], and the lowest priority interrupt is located - * at picIsrTable[picIsrTblPtr-1]. + * located at picPrioTable[0], and the lowest priority interrupt is located + * at picPrioTable[picPrioTblPtr-1]. * * */ -/* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */ -static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={ +#define DynamicIsrTable +#ifdef DynamicIsrTable +/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ +static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, @@ -121,7 +124,19 @@ static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; - +#else +static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ + 80, 84, 76, 77, 32, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1 }; +#endif /* * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ @@ -143,28 +158,18 @@ static inline int is_processor_irq(const rtems_irq_number irqLine) ); } -static inline unsigned int divIrq32(unsigned irq) -{ - return(irq/32); -} - -static inline unsigned int modIrq32(unsigned irq) -{ - return(irq%32); -} - /* * ------------------------ RTEMS Irq helper functions ---------------- */ /* - * Caution : this function assumes the variable "internal_config" + * Caution : this function assumes the variable "BSP_config" * is already set and that the tables it contains are still valid * and accessible. */ static void compute_pic_masks_from_prio() { - int i,j, k; + int i,j, k, isGppMain; unsigned long long irq_prio_mask=0; /* @@ -180,26 +185,27 @@ static void compute_pic_masks_from_prio() BSP_irq_prio_mask_tbl[k][i]=0; irq_prio_mask =0; + isGppMain =1; break; default : + isGppMain =0; irq_prio_mask = (unsigned long long) (1LLU << i); break; } - - if (irq_prio_mask) { + if ( isGppMain) continue; for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) { /* * Mask interrupts at PIC level that have a lower priority * or <Till Straumann> a equal priority. */ - if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j]) + if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j]) irq_prio_mask |= (unsigned long long)(1LLU << j); } BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff; BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff; -#ifdef DEBUG +#if 0 printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i], BSP_irq_prio_mask_tbl[0][i]); #endif @@ -207,17 +213,18 @@ static void compute_pic_masks_from_prio() BSP_irq_prio_mask_tbl[2][i] = 1<<i; /* Compute for the GPP priority interrupt mask */ for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) { - if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j]) + if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j]) BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET); } - } +#if 0 + printk("GPPirq_mask_prio_tbl[%d]:0x%8x\n",i,BSP_irq_prio_mask_tbl[2][i]); +#endif } } - static void UpdateMainIrqTbl(int irqNum) { - int i=0, j, shifted=0; + int i=0, j, k, shifted=0; switch (irqNum) { case BSP_MAIN_GPP7_0_IRQ: @@ -237,23 +244,25 @@ static void UpdateMainIrqTbl(int irqNum) ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))) { - while ( picIsrTable[i]!=-1) { - if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) { + while ( picPrioTable[i]!=-1) { + if (BSP_config.irqPrioTbl[irqNum]>BSP_config.irqPrioTbl[picPrioTable[i]]) { /* all other lower priority entries shifted right */ - for (j=picIsrTblPtr;j>i; j--) - picIsrTable[j]=picIsrTable[j-1]; - picIsrTable[i]=irqNum; + for (j=picPrioTblPtr;j>i; j--) { + picPrioTable[j]=picPrioTable[j-1]; + } + picPrioTable[i]=irqNum; shifted=1; break; } i++; } - if (!shifted) picIsrTable[picIsrTblPtr]=irqNum; + if (!shifted) picPrioTable[picPrioTblPtr] =irqNum; + if (irqNum >BSP_MICH_IRQ_MAX_OFFSET) GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); else MainIrqInTbl |= (unsigned long long)(1LLU << irqNum); - picIsrTblPtr++; + picPrioTblPtr++; } #ifdef SHOW_MORE_INIT_SETTINGS val2 = (MainIrqInTbl>>32) & 0xffffffff; @@ -267,7 +276,7 @@ static void UpdateMainIrqTbl(int irqNum) static void CleanMainIrqTbl(int irqNum) { - int i, j; + int i, j, k; switch (irqNum) { case BSP_MAIN_GPP7_0_IRQ: @@ -283,84 +292,96 @@ static void CleanMainIrqTbl(int irqNum) (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))) { /* If entry in table*/ for (i=0; i<64; i++) { - if (picIsrTable[i]==irqNum) {/*remove it from the entry */ + if (picPrioTable[i]==irqNum) {/*remove it from the entry */ /* all other lower priority entries shifted left */ - for (j=i;j<picIsrTblPtr; j++) - picIsrTable[j]=picIsrTable[j+1]; + for (j=i;j<picPrioTblPtr; j++) { + picPrioTable[j]=picPrioTable[j+1]; + } if (irqNum >BSP_MICH_IRQ_MAX_OFFSET) GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); else MainIrqInTbl &= ~(1LLU << irqNum); - picIsrTblPtr--; + picPrioTblPtr--; break; } } } } -void BSP_enable_pic_irq(const rtems_irq_number irqNum) +void BSP_enable_irq_at_pic(const rtems_irq_number irqNum) { unsigned bitNum, regNum; unsigned int level; - bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); - regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); + bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32; + regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5; rtems_interrupt_disable(level); +#ifdef DynamicIsrTable UpdateMainIrqTbl((int) irqNum); +#endif BSP_irqMask_cache[regNum] |= (1 << bitNum); out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); + memBar(); rtems_interrupt_enable(level); } -void BSP_disable_pic_irq(const rtems_irq_number irqNum) +void BSP_disable_irq_at_pic(const rtems_irq_number irqNum) { unsigned bitNum, regNum; unsigned int level; - bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); - regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); + bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32; + regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5; rtems_interrupt_disable(level); +#ifdef DynamicIsrTable CleanMainIrqTbl((int) irqNum); +#endif BSP_irqMask_cache[regNum] &= ~(1 << bitNum); out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); - + memBar(); rtems_interrupt_enable(level); } -int BSP_setup_the_pic() /* adapt the same name as shared/irq */ +/* Use shared/irq : 2008 */ +int BSP_setup_the_pic(rtems_irq_global_settings* config) { int i; - /* Get ready for discovery BSP */ - BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO); - BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI); - BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask); + BSP_config = *config; - BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO); - BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI); - BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause); + switch(BSP_getDiscoveryChipVersion()) { + case GT64260B: + case GT64260A: + /* Get ready for discovery BSP */ + BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO); + BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI); + BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO); + BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI); + break; + default: + printk("Not supported by this BSP yet\n"); + return(0); + break; + } -#ifdef EDGE_TRIGGER + BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask); + BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value); /* Page 401, Table 598: * Comm Unit Arbiter Control register : * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0). - * We set the GPP interrupts to be edge sensitive. - * MOTload default is set as level sensitive(1). + * MOTload default is set as level sensitive(1). Set it agin to make sure. */ - outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl); -#else outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl); -#endif #if 0 printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", @@ -374,7 +395,7 @@ int BSP_setup_the_pic() /* adapt the same name as shared/irq */ in_le32(BSP_irqCause_reg[2])); #endif - /* Initialize the interrupt related GT64260 registers */ + /* Initialize the interrupt related registers */ for (i=0; i<3; i++) { out_le32(BSP_irqCause_reg[i], 0); out_le32(BSP_irqMask_reg[i], 0); @@ -398,186 +419,21 @@ int BSP_setup_the_pic() /* adapt the same name as shared/irq */ * */ for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) { - if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { - BSP_enable_pic_irq(i); - rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); + if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) { + BSP_enable_irq_at_pic(i); + BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]); } else { - rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); - BSP_disable_pic_irq(i); + BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]); + BSP_disable_irq_at_pic(i); } } - - return(1); -} - -/* - * This function check that the value given for the irq line - * is valid. - */ - -static int isValidInterrupt(int irq) -{ - if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) - return 0; - return 1; -} - -/* - * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- - */ - -int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) -{ - unsigned int level; - - if (!isValidInterrupt(irq->name)) { - printk("Invalid interrupt vector %d\n",irq->name); - return 0; - } - /* - * Check if default handler is actually connected. If not issue an error. - * You must first get the current handler via i386_get_current_idt_entry - * and then disconnect it using i386_delete_idt_entry. - * RATIONALE : to always have the same transition by forcing the user - * to get the previous handler before accepting to disconnect. - */ - rtems_interrupt_disable(level); - if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { - rtems_interrupt_enable(level); - printk("IRQ vector %d already connected\n",irq->name); - return 0; - } - - /* - * store the data provided by user - */ - rtems_hdl_tbl[irq->name] = *irq; -#ifdef BSP_SHARED_HANDLER_SUPPORT - rtems_hdl_tbl[irq->name].next_handler = (void *)-1; -#endif - - if (is_pic_irq(irq->name)) { - /* - * Enable PIC irq : Main Interrupt Cause Low and High & GPP external - */ -#ifdef DEBUG_IRQ - printk("PIC irq %d\n",irq->name); -#endif - BSP_enable_pic_irq(irq->name); - } - else { - if (is_processor_irq(irq->name)) { - /* - * Enable exception at processor level - */ - - } - } - /* - * Enable interrupt on device - */ - irq->on(irq); + for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++) + BSP_enable_irq_at_pic(i); - rtems_interrupt_enable(level); - - return 1; -} - - -int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) -{ - if (!isValidInterrupt(irq->name)) { - return 0; - } - *irq = rtems_hdl_tbl[irq->name]; - return 1; -} - -int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) -{ - unsigned int level; - - if (!isValidInterrupt(irq->name)) { - return 0; - } - /* - * Check if default handler is actually connected. If not issue an error. - * You must first get the current handler via i386_get_current_idt_entry - * and then disconnect it using i386_delete_idt_entry. - * RATIONALE : to always have the same transition by forcing the user - * to get the previous handler before accepting to disconnect. - */ - if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { - return 0; - } - rtems_interrupt_disable(level); - - /* - * disable PIC interrupt - */ - if (is_pic_irq(irq->name)) - BSP_disable_pic_irq(irq->name); - else { - if (is_processor_irq(irq->name)) { - /* - * disable exception at processor level - */ - } - } - - /* - * Disable interrupt on device - */ - irq->off(irq); - - /* - * restore the default irq value - */ - rtems_hdl_tbl[irq->name] = default_rtems_entry; - - - rtems_interrupt_enable(level); - - return 1; -} - -/* - * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- - */ - -int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) -{ - unsigned int level; - int i; - - /* - * Store various code accelerators - */ - internal_config = config; - default_rtems_entry = config->defaultEntry; - rtems_hdl_tbl = config->irqHdlTbl; - - rtems_interrupt_disable(level); - - if ( !BSP_setup_the_pic() ) { - printk("PIC setup failed; leaving IRQs OFF\n"); - return 0; - } - - for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++) - BSP_enable_pic_irq(i); - - rtems_interrupt_enable(level); - return 1; + return(1); } -int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) -{ - *config = internal_config; - return 0; -} - /* * High level IRQ handler called from shared_raw_irq_code_entry */ @@ -586,85 +442,62 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) { register unsigned msr, new_msr; unsigned long irqCause[3]={0, 0,0}; - register unsigned long selectCause; unsigned oldMask[3]={0,0,0}; - register unsigned i=0, j, irq=0, bitmask=0, group=0; + int loop=0, wloop=0, i=0, j; + register irq=0, group=0; if (excNum == ASM_DEC_VECTOR) { _MSR_GET(msr); new_msr = msr | MSR_EE; _MSR_SET(new_msr); - rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle); - + BSP_config.irqHdlTbl[BSP_DECREMENTER].hdl(BSP_config.irqHdlTbl[BSP_DECREMENTER].handle); _MSR_SET(msr); return; } for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j]; + for (j=0; j<3; j++) irqCause[j] = in_le32(BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]); - if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){ - irqCause[1] = (selectCause & BSP_irqMask_cache[1]); - irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2]; - } - else { - irqCause[0] = (selectCause & BSP_irqMask_cache[0]); - if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1]))) - irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2]; - } - - while ((irq = picIsrTable[i++])!=-1) - { - if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) { + while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP)) + { + if (irqCause[group= irq/32] & ( 1<<(irq % 32))) { for (j=0; j<3; j++) BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]); - RTEMS_COMPILER_MEMORY_BARRIER(); - out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]); - out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]); - out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]); - in_le32((volatile unsigned *)0xf100f10c); - -#ifdef EDGE_TRIGGER - if (irq > BSP_MICH_IRQ_MAX_OFFSET) - out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */ -#endif - + out_le32(BSP_irqMask_reg[0], BSP_irqMask_cache[0]); + out_le32(BSP_irqMask_reg[1], BSP_irqMask_cache[1]); + out_le32(BSP_irqMask_reg[2], BSP_irqMask_cache[2]); + in_le32(BSP_irqMask_reg[2]); + _MSR_GET(msr); new_msr = msr | MSR_EE; _MSR_SET(new_msr); - rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); + /* handler */ +#ifdef BSP_SHARED_HANDLER_SUPPORT + { + rtems_irq_connect_data* vchain; + for( vchain = &BSP_config.irqHdlTbl[irq]; + (vchain->hdl != BSP_config.defaultEntry.hdl && ((int)vchain != -1) ); + vchain = (rtems_irq_connect_data*)vchain->next_handler ) + { + vchain->hdl(vchain->handle); + } + } +#else + BSP_config.irqHdlTbl[irq].hdl(BSP_config.irqHdlTbl[irq].handle); +#endif _MSR_SET(msr); - + for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j]; - break; + + out_le32(BSP_irqMask_reg[0], oldMask[0]); + out_le32(BSP_irqMask_reg[1], oldMask[1]); + out_le32(BSP_irqMask_reg[2], oldMask[2]); + in_le32(BSP_irqMask_reg[2]); } } - - out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]); - out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]); - out_le32((volatile unsigned *)0xf100f10c, oldMask[2]); - in_le32((volatile unsigned *)0xf100f10c); -} - -void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) -{ - /* - * Process pending signals that have not already been - * processed by _Thread_Displatch. This happens quite - * unfrequently : the ISR must have posted an action - * to the current running thread. - */ - if ( _Thread_Do_post_task_switch_extension || - _Thread_Executing->do_post_task_switch_extension ) { - _Thread_Executing->do_post_task_switch_extension = FALSE; - _API_extensions_Run_postswitch(); - } - /* - * I plan to process other thread related events here. - * This will include DEBUG session requested from keyboard... - */ } /* Only print part of the entries for now */ @@ -672,10 +505,10 @@ void BSP_printPicIsrTbl() { int i; - printk("picIsrTable[12]={"); + printf("picPrioTable[12]={ irq# :"); for (i=0; i<12; i++) - printk("%d,", picIsrTable[i]); - printk("}\n"); + printf("%d,", picPrioTable[i]); + printf("}\n"); - printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl); + printf("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl); } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h index 9b7c21367e..40b7f8c970 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h @@ -29,7 +29,8 @@ #ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H #define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H -/*#define BSP_SHARED_HANDLER_SUPPORT 1*/ +#define BSP_SHARED_HANDLER_SUPPORT 1 + #include <rtems/irq.h> #define BSP_ASM_IRQ_VECTOR_BASE 0x0 @@ -84,11 +85,11 @@ /* * Summary */ -#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_IRQ_NUMBER (BSP_PIC_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER) #define BSP_MAIN_IRQ_NUMBER (64) #define BSP_PIC_IRQ_NUMBER (96) -#define BSP_LOWEST_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) +#define BSP_LOWEST_OFFSET (0) +#define BSP_MAX_OFFSET (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1) /* Main CPU interrupt cause (Low) */ #define BSP_MAIN_TIMER0_1_IRQ (BSP_MICL_IRQ_LOWEST_OFFSET+8) diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c index a56158067f..ebdd9a8b46 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c @@ -41,10 +41,18 @@ static int connected() {return 1;} static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; static rtems_irq_global_settings initial_config; + +#ifdef BSP_SHARED_HANDLER_SUPPORT +static rtems_irq_connect_data defaultIrq = { + /* vectorIdex, hdl ,handle , on , off , isOn ,next_handler, */ + 0, nop_func , NULL , nop_func , nop_func , not_connected, 0 +}; +#else static rtems_irq_connect_data defaultIrq = { /* vectorIdex, hdl , handle , on , off , isOn */ 0, nop_func , NULL , nop_func , nop_func , not_connected }; +#endif rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={ /* @@ -140,27 +148,6 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) printk("Done setup irq mngt configuration\n"); #endif - /* - * We must connect the raw irq handler for the two - * expected interrupt sources : decrementer and external interrupts. - */ - vectorDesc.exceptIndex = ASM_DEC_VECTOR; - vectorDesc.hdl.vector = ASM_DEC_VECTOR; - vectorDesc.hdl.raw_hdl = decrementer_exception_vector_prolog_code; - vectorDesc.hdl.raw_hdl_size = (unsigned) decrementer_exception_vector_prolog_code_size; - vectorDesc.on = nop_func; - vectorDesc.off = nop_func; - vectorDesc.isOn = connected; - if (!ppc_set_exception (&vectorDesc)) { - BSP_panic("Unable to initialize RTEMS decrementer raw exception\n"); - } - vectorDesc.exceptIndex = ASM_EXT_VECTOR; - vectorDesc.hdl.vector = ASM_EXT_VECTOR; - vectorDesc.hdl.raw_hdl = external_exception_vector_prolog_code; - vectorDesc.hdl.raw_hdl_size = (unsigned) external_exception_vector_prolog_code_size; - if (!ppc_set_exception (&vectorDesc)) { - BSP_panic("Unable to initialize RTEMS external raw exception\n"); - } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif diff --git a/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c b/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c index de3448655a..483b0d00d9 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c @@ -2,23 +2,16 @@ * * Copyright (c) 2003,2004 Brookhaven National Laboratory * S. Kate Feng <feng1@bnl.gov> - * All rights reserved + * All rights reserved * * Acknowledgements: * netBSD : Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. * Marvell : NDA document for the discovery system controller - * The author referenced two RTEMS network drivers of other NICs. - * rtems : 1) dec21140.c, a network driver for for TULIP based Ethernet Controller - * (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr - * - * 2) yellowfin.c, a network driver for the SVGM5 BSP. - * Stanford Linear Accelerator Center, Till Straumann * * Some notes from the author, S. Kate Feng : * * 1) Mvme5500 uses Eth0 (controller 0) of the GT64260 to implement - * the 10/100 BaseT Ethernet with PCI Master Data Byte Swap\ - * control. + * the 10/100 BaseT Ethernet with PCI Master Data Byte Swap control. * 2) Implemented hardware snoop instead of software snoop * to ensure SDRAM cache coherency. (Copyright : NDA item) * 3) Added S/W support for multi mbuf. (TODO : Let the H/W do it) @@ -55,6 +48,7 @@ #include <sys/sockio.h> /* SIOCADDMULTI, SIOC... */ #include <net/if.h> #include <net/if_dl.h> +#include <net/ethernet.h> #include <netinet/in.h> #include <netinet/if_ether.h> @@ -110,7 +104,7 @@ enum GTeth_hash_op { #define ET_MINLEN 64 /* minimum message length */ -static int GTeth_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data); +static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data); static void GTeth_ifstart (struct ifnet *); static void GTeth_ifchange(struct GTeth_softc *sc); static void GTeth_init_rx_ring(struct GTeth_softc *sc); @@ -169,8 +163,8 @@ static void GT64260eth_isr() outl( ~cause,ETH0_EICR); /* clear the ICR */ if ( (!cause) || (cause & 0x803d00)) { - sc->intr_errsts[sc->intr_err_ptr2++]=cause; - sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */ + sc->if_errsts[sc->if_err_ptr2]=cause; + if ( (++sc->if_err_ptr2) == IF_ERR_BUFSZE) sc->if_err_ptr2=0; /* Till Straumann */ events |= ERR_EVENT; } @@ -201,7 +195,7 @@ static void GT64260eth_isr() static rtems_irq_connect_data GT64260ethIrqData={ BSP_MAIN_ETH0_IRQ, (rtems_irq_hdl) GT64260eth_isr, - NULL, + (rtems_irq_hdl_param) NULL, (rtems_irq_enable) GT64260eth_irq_on, (rtems_irq_disable) GT64260eth_irq_off, (rtems_irq_is_enabled) GT64260eth_irq_is_on, @@ -330,20 +324,15 @@ static void GT64260eth_ifinit(void *arg) GTeth_hash_fill(sc); #endif - sc->intr_err_ptr1=0; - sc->intr_err_ptr2=0; - for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0; + sc->if_err_ptr1=0; + sc->if_err_ptr2=0; + for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0; /* initialize the hardware (we are holding the network semaphore at this point) */ (void)GT64260eth_init_hw(sc); /* launch network daemon */ - - /* NOTE: - * in ss-20011025 (and later) any task created by 'bsdnet_newproc' is - * wrapped by code which acquires the network semaphore... - */ - sc->daemonTid = rtems_bsdnet_newproc(GT_ETH_TASK_NAME,4096,GT64260eth_daemon,arg); + sc->daemonTid = rtems_bsdnet_newproc(GT_ETH_TASK_NAME,4096,GT64260eth_daemon,arg); /* Tell the world that we're running */ sc->arpcom.ac_if.if_flags |= IFF_RUNNING; @@ -364,9 +353,11 @@ int rtems_GT64260eth_driver_attach(struct rtems_bsdnet_ifconfig *config, int att unit = rtems_bsdnet_parse_driver_name(config, &name); if (unit < 0) return 0; - - printk("\nEthernet driver name %s unit %d \n",name, unit); - printk("(c) 2004, Brookhaven National Lab. <feng1@bnl.gov> (RTEMS/mvme5500 port)\n"); + if ( !strncmp((const char *)name,"autoz",5)) + memcpy(name,"gtMHz",5); + + printk("\nAttaching GT64260 built-in 10/100 MHz NIC%d\n", unit); + printk("RTEMS-mvme5500 BSP Copyright (c) 2004, Brookhaven National Lab., Shuchen Kate Feng\n"); /* Make certain elements e.g. descriptor lists are aligned. */ softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT); @@ -388,31 +379,25 @@ int rtems_GT64260eth_driver_attach(struct rtems_bsdnet_ifconfig *config, int att /* try to read HW address from the device if not overridden * by config */ - if (config->hardware_address) { - memcpy(hwaddr, config->hardware_address, ETHER_ADDR_LEN); - } else { - printk("Read EEPROM "); - for (i = 0; i < 6; i++) - hwaddr[i] = ConfVPD_buff[VPD_ENET0_OFFSET+i]; - } + if (config->hardware_address) + memcpy((void *)sc->arpcom.ac_enaddr,(const void *) config->hardware_address, ETHER_ADDR_LEN); + else + memcpy((void *)sc->arpcom.ac_enaddr, (const void *) &ConfVPD_buff[VPD_ENET0_OFFSET], ETHER_ADDR_LEN); #ifdef GT_DEBUG printk("using MAC addr from device:"); - for (i = 0; i < ETHER_ADDR_LEN; i++) printk("%x:", hwaddr[i]); + for (i = 0; i < ETHER_ADDR_LEN; i++) printk("%x:", sc->arpcom.ac_enaddr[i]); printk("\n"); #endif - memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN); - ifp = &sc->arpcom.ac_if; sc->sc_pcr = inl(ETH0_EPCR); sc->sc_pcxr = inl(ETH0_EPCXR); sc->sc_intrmask = inl(ETH0_EIMR) | ETH_IR_MIIPhySTC; - printk("address %s\n", ether_sprintf(hwaddr)); - #ifdef GT_DEBUG + printk("address %s\n", ether_sprintf(hwaddr)); printk(", pcr %x, pcxr %x ", sc->sc_pcr, sc->sc_pcxr); #endif @@ -511,7 +496,6 @@ static void GT64260eth_stats(struct GTeth_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; -#if 0 printf(" Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts); printf(" Receive Packets:%-8lu\n", ifp->if_ipackets); printf(" Receive errors:%-8lu\n", ifp->if_ierrors); @@ -520,18 +504,10 @@ static void GT64260eth_stats(struct GTeth_softc *sc) printf(" Oversized Frames:%-8lu\n", sc->stats.length_errors); printf(" Active Rxqs:%-8u\n", sc->rxq_active); printf(" Tx Interrupts:%-8lu\n", sc->stats.txInterrupts); -#endif - printf("Multi-BuffTx Packets:%-8lu\n", sc->stats.txMultiBuffPacket); - printf("Multi-BuffTx max len:%-8lu\n", sc->stats.txMultiMaxLen); - printf("SingleBuffTx max len:%-8lu\n", sc->stats.txSinglMaxLen); - printf("Multi-BuffTx maxloop:%-8lu\n", sc->stats.txMultiMaxLoop); - printf("Tx buffer max len :%-8lu\n", sc->stats.txBuffMaxLen); -#if 0 printf(" Transmitt Packets:%-8lu\n", ifp->if_opackets); printf(" Transmitt errors:%-8lu\n", ifp->if_oerrors); printf(" Tx/Rx collisions:%-8lu\n", ifp->if_collisions); printf(" Active Txqs:%-8u\n", sc->txq_nactive); -#endif } void GT64260eth_printStats() @@ -539,7 +515,7 @@ void GT64260eth_printStats() GT64260eth_stats(root_GT64260eth_dev); } -static int GTeth_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data) { struct GTeth_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *) data; @@ -585,7 +561,7 @@ static int GTeth_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) if (error == ENETRESET) { if (ifp->if_flags & IFF_RUNNING) GTeth_ifchange(sc); - else + else error = 0; } break; @@ -862,6 +838,7 @@ static void GTeth_txq_free(struct GTeth_softc *sc, unsigned cmdsts) --sc->txq_nactive; } +#if 0 static int txq_high_limit(struct GTeth_softc *sc) { /* @@ -901,6 +878,7 @@ static int txq_high_limit(struct GTeth_softc *sc) } /* end if ( TX_RING_SIZE == sc->txq_nactive + TXQ_HiLmt_OFF) */ return 0; } +#endif static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m) { @@ -916,10 +894,8 @@ static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m) */ intrmask = sc->sc_intrmask; - if ( !(m->m_next)) {/* single buffer packet */ + if ( !(m->m_next)) /* single buffer packet */ sc->txq_mbuf[index]= m; - sc->stats.txSinglMaxLen= MAX(m->m_len, sc->stats.txSinglMaxLen); - } else /* multiple mbufs in this packet */ { struct mbuf *mtp, *mdest; @@ -947,9 +923,7 @@ static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m) printk("%d ",mtp->m_len); #endif len += mtp->m_len; - sc->stats.txBuffMaxLen=MAX(mtp->m_len,sc->stats.txBuffMaxLen); } - sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop); #if 0 printk("\n"); #endif @@ -957,8 +931,6 @@ static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m) /* free old mbuf chain */ m_freem(m); sc->txq_mbuf[index] = m = mdest; - sc->stats.txMultiBuffPacket++; - sc->stats.txMultiMaxLen= MAX(m->m_len, sc->stats.txMultiMaxLen); } if (m->m_len < ET_MINLEN) m->m_len = ET_MINLEN; @@ -1137,12 +1109,10 @@ static void GTeth_tx_stop(struct GTeth_softc *sc) sc->arpcom.ac_if.if_timer = 0; } -/* TOCHECK : Should it be about rx or tx ? */ static void GTeth_ifchange(struct GTeth_softc *sc) { if (GTeth_debug>0) printk("GTeth_ifchange("); if (GTeth_debug>5) printk("(pcr=%#x,imr=%#x)",inl(ETH0_EPCR),inl(ETH0_EIMR)); - /* printk("SIOCADDMULTI (SIOCDELMULTI): is it about rx or tx ?\n");*/ outl(sc->sc_pcr | ETH_EPCR_EN, ETH0_EPCR); outl(sc->sc_intrmask, ETH0_EIMR); GTeth_ifstart(&sc->arpcom.ac_if); @@ -1445,10 +1415,11 @@ static void GTeth_hash_init(struct GTeth_softc *sc) #endif } +#ifdef GT64260eth_DEBUG static void GT64260eth_error(struct GTeth_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - unsigned int intr_status= sc->intr_errsts[sc->intr_err_ptr1]; + unsigned int intr_status= sc->if_errsts[sc->if_err_ptr1]; /* read and reset the status; because this is written * by the ISR, we must disable interrupts here @@ -1471,10 +1442,10 @@ static void GT64260eth_error(struct GTeth_softc *sc) else printk("%s%d: Ghost interrupt ?\n",ifp->if_name, ifp->if_unit); - sc->intr_errsts[sc->intr_err_ptr1++]=0; - sc->intr_err_ptr1 %= INTR_ERR_SIZE; /* Till Straumann */ + sc->if_errsts[sc->if_err_ptr1]=0; + if ( (++sc->if_err_ptr1) == IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */ } - +#endif /* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */ static void GT64260eth_daemon(void *arg) @@ -1484,13 +1455,6 @@ static void GT64260eth_daemon(void *arg) struct mbuf *m=0; struct ifnet *ifp=&sc->arpcom.ac_if; -#if 0 - /* see comments in GT64260eth_init(); in newer versions of - * rtems, we hold the network semaphore at this point - */ - rtems_semaphore_release(sc->daemonSync); -#endif - /* NOTE: our creator possibly holds the bsdnet_semaphore. * since that has PRIORITY_INVERSION enabled, our * subsequent call to bsdnet_event_receive() will @@ -1548,7 +1512,9 @@ static void GT64260eth_daemon(void *arg) ifp->if_flags &= ~IFF_OACTIVE; /* Log errors and other uncommon events. */ - if (events & ERR_EVENT) GT64260eth_error(sc); +#ifdef GT64260eth_DEBUG + if (events & ERR_EVENT) GT64260eth_error(sc); +#endif } /* end for(;;) { rtems_bsdnet_event_receive() .....*/ ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); diff --git a/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.h b/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.h index 52ea42c39e..144937d9a3 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.h @@ -4,6 +4,7 @@ * All rights reserved. * * RTEMS/Mvme5500 port 2004 by S. Kate Feng, <feng1@bnl.gov>, + * under the Deaprtment of Energy contract DE-AC02-98CH10886 * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -50,7 +51,7 @@ #define RX_RING_SIZE 16 #define HASH_TABLE_SIZE 16 #define HASH_DRAM_SIZE HASH_TABLE_SIZE*1024 /* size of DRAM for hash table */ -#define INTR_ERR_SIZE 16 +#define IF_ERR_BUFSZE 16 enum GTeth_txprio { GE_TXPRIO_HI=1, @@ -70,9 +71,9 @@ struct GTeth_softc { struct mbuf* txq_mbuf[TX_RING_SIZE]; /* transmit buffer memory */ struct mbuf* rxq_mbuf[RX_RING_SIZE]; /* receive buffer memory */ struct GTeth_softc *next_module; - volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* capture the right intr_status */ - unsigned int intr_err_ptr1; /* ptr used in GTeth_error() */ - unsigned int intr_err_ptr2; /* ptr used in ISR */ + volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* capture the right intr_status */ + unsigned int if_err_ptr1; /* ptr used in GTeth_error() */ + unsigned int if_err_ptr2; /* ptr used in ISR */ struct ifqueue txq_pendq; /* these are ready to go to the GT */ unsigned int txq_pending; unsigned int txq_lo; /* next to be given to GT DMA */ @@ -125,13 +126,7 @@ struct GTeth_softc { /* statistics */ struct { volatile unsigned long rxInterrupts; - volatile unsigned long txInterrupts; - unsigned long txMultiBuffPacket; - unsigned long txMultiMaxLen; - unsigned long txSinglMaxLen; - unsigned long txMultiMaxLoop; - unsigned long txBuffMaxLen; unsigned long length_errors; unsigned long frame_errors; unsigned long crc_errors; diff --git a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c index 453da7d9b1..3cef5eb1fd 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov> + * Copyright (c) 2004,2005, 2008 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov> + * under the Deaprtment of Energy contract DE-AC02-98CH10886 * Brookhaven National Laboratory, All rights reserved * * Acknowledgements: @@ -25,8 +26,7 @@ * hardware auto-neg. state machine disabled. PCI control "snoop * to WB region", MII mode (PHY) instead of TBI mode. * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing. - * 7) Support for checksum offloading and TCP segmentation offload will - * be available for releasing in 2008, upon request, if I still believe. + * 7) Implementation for Jumbo Frame and TCP checksum is not yet completed. * */ @@ -34,8 +34,11 @@ #define INET +/*#define RTEMS_ETHERMTU_JUMBO*/ + #include <rtems.h> #include <rtems/bspIo.h> /* printk */ + #include <stdio.h> /* printf for statistics */ #include <string.h> @@ -64,6 +67,7 @@ #include <net/if_dl.h> #include <netinet/in.h> #include <netinet/if_ether.h> +#include <net/ethernet.h> #ifdef INET #include <netinet/in_var.h> @@ -82,7 +86,7 @@ #define i82544EI_TASK_NAME "IGHZ" #define SOFTC_ALIGN 4095 -#define INTR_ERR_SIZE 16 +#define IF_ERR_BUFSZE 16 /*#define WM_DEBUG*/ #ifdef WM_DEBUG @@ -109,12 +113,12 @@ int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; #define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT) - -#define NTXDESC 128 +/* <skf> used 64 in 4.8.0, TOD; try 4096 */ +#define NTXDESC 256 #define NTXDESC_MASK (NTXDESC - 1) #define WM_NEXTTX(x) (((x) + 1) & NTXDESC_MASK) -#define NRXDESC 64 +#define NRXDESC 256 #define NRXDESC_MASK (NRXDESC - 1) #define WM_NEXTRX(x) (((x) + 1) & NRXDESC_MASK) #define WM_PREVRX(x) (((x) - 1) & NRXDESC_MASK) @@ -123,9 +127,10 @@ int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; #define WM_CDTXOFF(x) WM_CDOFF(sc_txdescs[(x)]) #define WM_CDRXOFF(x) WM_CDOFF(sc_rxdescs[(x)]) -#define TXQ_HiLmt_OFF 64 +#define TXQ_HiLmt_OFF 32 static uint32_t TxDescCmd; +static unsigned BSP_1GHz_membase; /* * Software state per device. @@ -136,9 +141,9 @@ struct wm_softc { struct mbuf *txs_mbuf[NTXDESC]; /* transmit buffer memory */ struct mbuf *rxs_mbuf[NRXDESC]; /* receive buffer memory */ struct wm_softc *next_module; - volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* intr_status */ - unsigned int intr_err_ptr1; /* ptr used in i82544EI_error() */ - unsigned int intr_err_ptr2; /* ptr used in ISR */ + volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* intr_status */ + unsigned int if_err_ptr1; /* ptr used in i82544EI_error() */ + unsigned int if_err_ptr2; /* ptr used in ISR */ int txs_firstdesc; /* first descriptor in packet */ int txs_lastdesc; /* last descriptor in packet */ int txs_ndesc; /* # of descriptors used */ @@ -168,15 +173,16 @@ struct wm_softc { int sc_rxptr; /* next ready Rx descriptor/queue ent */ int sc_rxdiscard; int sc_rxlen; + uint32_t sc_ctrl; /* prototype CTRL register */ -#if 0 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ -#endif + uint32_t sc_icr; /* prototype interrupt bits */ uint32_t sc_tctl; /* prototype TCTL register */ uint32_t sc_rctl; /* prototype RCTL register */ uint32_t sc_tipg; /* prototype TIPG register */ uint32_t sc_fcrtl; /* prototype FCRTL register */ + uint32_t sc_pba; /* prototype PBA register */ int sc_mchash_type; /* multicast filter offset */ @@ -184,11 +190,6 @@ struct wm_softc { struct { volatile unsigned long rxInterrupts; volatile unsigned long txInterrupts; - unsigned long txMultiBuffPacket; - unsigned long txMultiMaxLen; - unsigned long txSinglMaxLen; - unsigned long txMultiMaxLoop; - unsigned long txBuffMaxLen; unsigned long linkInterrupts; unsigned long length_errors; unsigned long frame_errors; @@ -224,20 +225,20 @@ struct wm_softc { static struct wm_softc *root_i82544EI_dev = NULL; static void i82544EI_ifstart(struct ifnet *ifp); -static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data); +static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data); static void i82544EI_ifinit(void *arg); static void wm_stop(struct ifnet *ifp, int disable); +static void wm_gmii_mediainit(struct wm_softc *sc); static void wm_rxdrain(struct wm_softc *sc); static int wm_add_rxbuf(struct wm_softc *sc, int idx); static int wm_read_eeprom(struct wm_softc *sc,int word,int wordcnt, uint16_t *data); static void i82544EI_daemon(void *arg); static void wm_set_filter(struct wm_softc *sc); - -static void i82544EI_isr(); +static void i82544EI_rx(struct wm_softc *sc); +static void i82544EI_isr(rtems_irq_hdl_param handle); static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m); extern int pci_mem_find(), pci_io_find(), pci_get_capability(); -extern char * ether_sprintf1(); static void i82544EI_irq_on(const rtems_irq_connect_data *irq) { @@ -269,6 +270,7 @@ static int i82544EI_irq_is_on(const rtems_irq_connect_data *irq) static rtems_irq_connect_data i82544IrqData={ BSP_GPP_82544_IRQ, (rtems_irq_hdl) i82544EI_isr, + (rtems_irq_hdl_param) NULL, (rtems_irq_enable) i82544EI_irq_on, (rtems_irq_disable) i82544EI_irq_off, (rtems_irq_is_enabled) i82544EI_irq_is_on, @@ -288,9 +290,12 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac unit = rtems_bsdnet_parse_driver_name(config, &name); if (unit < 0) return 0; - - printk("\nEthernet driver name %s unit %d \n",name, unit); - printk("Copyright (c) 2004,2005 S. Kate Feng <feng1@bnl.gov> (RTEMS/mvme5500 port)\n"); + + if ( !strncmp((const char *)name,"autoz",5)) + memcpy(name,"gtGHz",5); + + printk("\nAttaching MVME5500 1GHz NIC%d\n", unit); + printk("RTEMS-mvme5500 BSP Copyright (c) 2004,2005,2008 Shuchen Kate Feng \n"); /* Make sure certain elements e.g. descriptor lists are aligned.*/ softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT); @@ -316,13 +321,16 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac if ( pci_mem_find(b,d,f,PCI_MAPREG_START, &sc->sc_membase, &sc->sc_memsize)) rtems_panic("i82544EI: unable to map memory space\n"); + printk("Memory base addr 0x%x\n", sc->sc_membase); + BSP_1GHz_membase= sc->sc_membase; + #ifdef WM_DEBUG printk("Memory base addr 0x%x\n", sc->sc_membase); printk("txdesc[0] addr:0x%x, rxdesc[0] addr:0x%x, sizeof sc %d\n",&sc->sc_txdescs[0], &sc->sc_rxdescs[0], sizeof(*sc)); #endif - sc->sc_ctrl |=CSR_READ(sc,WMREG_CTRL); + sc->sc_ctrl=CSR_READ(sc,WMREG_CTRL); /* * Determine a few things about the bus we're connected to. */ @@ -360,11 +368,10 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac enaddr[4] = myea[2] & 0xff; enaddr[5] = myea[2] >> 8; - memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN); #ifdef WM_DEBUG printk("%s: Ethernet address %s\n", sc->dv_xname, - ether_sprintf1(enaddr)); + ether_sprintf(enaddr)); #endif /* @@ -395,13 +402,39 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext); #endif + /* + * Determine if we're TBI or GMII mode, and initialize the + * media structures accordingly. + */ + if ((CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { + /* 1000BASE-X : fiber (TBI mode) + wm_tbi_mediainit(sc); */ + } else { /* 1000BASE-T : copper (internal PHY mode), for the mvme5500 */ + wm_gmii_mediainit(sc); + } + ifp = &sc->arpcom.ac_if; /* set this interface's name and unit */ ifp->if_unit = unit; ifp->if_name = name; ifp->if_softc = sc; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; +#ifdef RTEMS_ETHERMTU_JUMBO + sc->arpcom.ec_capabilities |= ETHERCAP_JUMBO_MTU; + ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU_JUMBO; +#else ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU; +#endif +#ifdef RTEMS_CKSUM_OFFLOAD + /* < skf> The following is really not related to jumbo frame + sc->arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU;*/ + ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | + IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | + IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | + IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx | + IFCAP_TSOv4; /* TCP segmentation offload. */ +#endif + ifp->if_ioctl = wm_ioctl; ifp->if_start = i82544EI_ifstart; /* ifp->if_watchdog = wm_watchdog;*/ @@ -416,7 +449,8 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac rtems_build_name('I','G','H','Z'),0,0,0,&sc->daemonSync)) rtems_panic("i82544EI: semaphore creation failed"); - sc->next_module = root_i82544EI_dev; + i82544IrqData.handle= (rtems_irq_hdl_param) sc; + /* sc->next_module = root_i82544EI_dev;*/ root_i82544EI_dev = sc; /* Attach the interface. */ @@ -430,6 +464,39 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac } /* + * wm_reset: + * + * Reset the i82544 chip. + */ +static void wm_reset(struct wm_softc *sc) +{ + int i; + + sc->sc_pba = sc->arpcom.ac_if.if_mtu > 8192 ? PBA_40K : PBA_48K; + CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); + + /* device reset */ + CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); + rtems_bsp_delay(10000); + + for (i = 0; i < 1000; i++) { + if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) + break; + rtems_bsp_delay(20); + } + if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) + printk("Intel 82544 1GHz reset failed to complete\n"); + + sc->sc_ctrl_ext = CSR_READ(sc,WMREG_CTRL_EXT); + sc->sc_ctrl_ext |= CTRL_EXT_EE_RST; + CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); + CSR_READ(sc, WMREG_STATUS); + /* Wait for EEPROM reload */ + rtems_bsp_delay(2000); + sc->sc_ctrl= CSR_READ(sc, WMREG_CTRL); +} + +/* * i82544EI_ifstart: [ifnet interface function] * * Start packet transmission on the interface. @@ -461,27 +528,21 @@ static void i82544EI_stats(struct wm_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - printf(" Rx Interrupts:%-8u\n", sc->stats.rxInterrupts); + printf(" Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts); + printf(" Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts); printf(" Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC)); - printf(" Receive Overrun:%-8u\n", sc->stats.rxOvrRunInterrupts); + printf(" Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts); printf(" Receive errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC)); - printf(" Rx sequence error:%-8u\n", sc->stats.rxSeqErr); - printf(" Rx /C/ ordered:%-8u\n", sc->stats.rxC_ordered); + printf(" Rx sequence error:%-8lu\n", sc->stats.rxSeqErr); + printf(" Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered); printf(" Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC)); - printf(" Tx Interrupts:%-8u\n", sc->stats.txInterrupts); -#if 0 - printf("Multi-BuffTx Packets:%-8u\n", sc->stats.txMultiBuffPacket); - printf("Multi-BuffTx max len:%-8u\n", sc->stats.txMultiMaxLen); - printf("SingleBuffTx max len:%-8u\n", sc->stats.txSinglMaxLen); - printf("Multi-BuffTx maxloop:%-8u\n", sc->stats.txMultiMaxLoop); - printf("Tx buffer max len :%-8u\n", sc->stats.txBuffMaxLen); -#endif + printf(" Tx Interrupts:%-8lu\n", sc->stats.txInterrupts); printf(" Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC)); - printf(" Transmitt errors:%-8u\n", ifp->if_oerrors); - printf(" Active Txqs:%-8u\n", sc->txq_nactive); + printf(" Transmitt errors:%-8lu\n", ifp->if_oerrors); + printf(" Active Txqs:%-8lu\n", sc->txq_nactive); printf(" collisions:%-8u\n", CSR_READ(sc,WMREG_COLC)); printf(" Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS)); - printf(" Link Status Change:%-8u\n", sc->stats.linkStatusChng); + printf(" Link Status Change:%-8lu\n", sc->stats.linkStatusChng); } /* @@ -489,7 +550,7 @@ static void i82544EI_stats(struct wm_softc *sc) * * Handle control requests from the operator. */ -static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data) +static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data) { struct wm_softc *sc = ifp->if_softc; int error=0; @@ -521,9 +582,9 @@ static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data) * * Interrupt service routine. */ -static void i82544EI_isr() +static void i82544EI_isr(rtems_irq_hdl_param handle) { - volatile struct wm_softc *sc = root_i82544EI_dev; + volatile struct wm_softc *sc = (struct wm_softc *) handle; uint32_t icr; rtems_event_set events=0; @@ -547,8 +608,8 @@ static void i82544EI_isr() events |= INIT_EVENT; } if (icr & ICR_RXSEQ) /* framing error */ { - sc->intr_errsts[sc->intr_err_ptr2++]=icr; - sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */ + sc->if_errsts[sc->if_err_ptr2]=icr; + if ((++sc->if_err_ptr2)==IF_ERR_BUFSZE) sc->if_err_ptr2=0;/* Till Straumann */ events |= ERR_EVENT; sc->stats.rxSeqErr++; } @@ -606,15 +667,12 @@ static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m) * The other way is effective for packets < 2K */ if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) { - printk(">2048, use next descriptor\n"); + printk(" >%d, use next descriptor\n", sizeof(union mcluster)); break; } memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len); pt += mtp->m_len; len += mtp->m_len; -#if 0 - sc->stats.txSinglMaxLen= MAX(mtp->m_len, sc->stats.txSinglMaxLen); -#endif } /* end for loop */ mdest->m_len=len; sc->txs_mbuf[sc->txq_next] = mdest; @@ -628,15 +686,8 @@ static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m) sc->txq_free--; else rtems_panic("i8254EI : no more free descriptors"); -#if 0 - sc->stats.txMultiMaxLen= MAX(mdest->m_len, sc->stats.txMultiMaxLen); - sc->stats.txMultiBuffPacket++; -#endif } /* end for while */ /* free old mbuf chain */ -#if 0 - sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop); -#endif m_freem(m); m=0; } /* end multiple mbufs */ @@ -742,12 +793,11 @@ static void i82544EI_rx(struct wm_softc *sc) sc->dv_xname, i)); status = sc->sc_rxdescs[i].wrx_status; + if ((status & WRX_ST_DD) == 0) break; /* descriptor not done */ + errors = sc->sc_rxdescs[i].wrx_errors; len = le16toh(sc->sc_rxdescs[i].wrx_len); m = sc->rxs_mbuf[i]; - - if ((status & WRX_ST_DD) == 0) break; /* descriptor not done */ - if (sc->sc_rxdiscard) { printk("RX: discarding contents of descriptor %d\n", i); wm_init_rxdesc(sc, i); @@ -819,16 +869,46 @@ static int i82544EI_init_hw(struct wm_softc *sc) int i,error; uint8_t cksumfields; +#if 0 + /* KATETODO : sc_align_tweak */ + /* + * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. + * There is a small but measurable benefit to avoiding the adjusment + * of the descriptor so that the headers are aligned, for normal mtu, + * on such platforms. One possibility is that the DMA itself is + * slightly more efficient if the front of the entire packet (instead + * of the front of the headers) is aligned. + * + * Note we must always set align_tweak to 0 if we are using + * jumbo frames. + */ +#ifdef __NO_STRICT_ALIGNMENT + sc->sc_align_tweak = 0; +#else + if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) + sc->sc_align_tweak = 0; + else + sc->sc_align_tweak = 2; +#endif /* __NO_STRICT_ALIGNMENT */ +#endif + /* Cancel any pending I/O. */ wm_stop(ifp, 0); + /* update statistics before reset */ + ifp->if_collisions += CSR_READ(sc, WMREG_COLC); + ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); + + /* Reset the chip to a known state. */ + wm_reset(sc); + /* Initialize the error buffer ring */ - sc->intr_err_ptr1=0; - sc->intr_err_ptr2=0; - for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0; + sc->if_err_ptr1=0; + sc->if_err_ptr2=0; + for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0; /* Initialize the transmit descriptor ring. */ - memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); + memset( (void *) sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); sc->txq_free = NTXDESC; sc->txq_next = 0; sc->txs_lastdesc = 0; @@ -847,8 +927,8 @@ static int i82544EI_init_hw(struct wm_softc *sc) CSR_WRITE(sc,WMREG_TDLEN, sizeof(sc->sc_txdescs)); CSR_WRITE(sc,WMREG_TDH, 0); CSR_WRITE(sc,WMREG_TDT, 0); - CSR_WRITE(sc,WMREG_TIDV, 64 ); - CSR_WRITE(sc,WMREG_TADV, 128); + CSR_WRITE(sc,WMREG_TIDV, 0 ); + /* CSR_WRITE(sc,WMREG_TADV, 128); not for 82544 */ CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); @@ -862,10 +942,11 @@ static int i82544EI_init_hw(struct wm_softc *sc) * Set up checksum offload parameters for * this packet. */ -#ifdef CKSUM_OFFLOAD - if (m0->m_pkthdr.csum_flags & - (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { - if (wm_tx_cksum(sc, txs, &TxDescCmd,&cksumfields) != 0) { +#ifdef RTEMS_CKSUM_OFFLOAD + if (m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6| + M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| + M_CSUM_TCPv6|M_CSUM_UDPv6)) { + if (wm_tx_offload(sc, txs, &TxDescCmd,&cksumfields) != 0) { /* Error message already displayed. */ continue; } @@ -873,7 +954,7 @@ static int i82544EI_init_hw(struct wm_softc *sc) #endif TxDescCmd = 0; cksumfields = 0; -#ifdef CKSUM_OFFLOAD +#ifdef RTEMS_CKSUM_OFFLOAD } #endif @@ -892,14 +973,14 @@ static int i82544EI_init_hw(struct wm_softc *sc) * Initialize the receive descriptor and receive job * descriptor rings. */ - memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); + memset( (void *) sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); CSR_WRITE(sc,WMREG_RDBAH, 0); CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc)); CSR_WRITE(sc,WMREG_RDLEN, sizeof(sc->sc_rxdescs)); CSR_WRITE(sc,WMREG_RDH, 0); CSR_WRITE(sc,WMREG_RDT, 0); CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD); - CSR_WRITE(sc, WMREG_RADV, 256); + /* CSR_WRITE(sc, WMREG_RADV, 256); not for 82544. */ for (i = 0; i < NRXDESC; i++) { if (sc->rxs_mbuf[i] == NULL) { @@ -943,12 +1024,13 @@ static int i82544EI_init_hw(struct wm_softc *sc) CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT); CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl); - CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT); + /*KATETO CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);*/ + CSR_WRITE(sc,WMREG_FCTTV, 0x100); sc->sc_ctrl &= ~CTRL_VME; - /*sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;*/ - /* enable Big Endian Mode for the powerPC - sc->sc_ctrl |= CTRL_BEM;*/ + /* KATETODo : not here. + Configures flow control settings after link is established + sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE; */ /* Write the control registers. */ CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl); @@ -956,7 +1038,21 @@ static int i82544EI_init_hw(struct wm_softc *sc) CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext); #endif - /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ + /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ +#ifdef RTEMS_CKSUM_OFFLOAD + /* + * Set up checksum offload parameters. + */ + reg = CSR_READ(sc, WMREG_RXCSUM); + reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL); + if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) + reg |= RXCSUM_IPOFL; + if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) + reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; + if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) + reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL; + CSR_WRITE(sc, WMREG_RXCSUM, reg); +#endif /* * Set up the interrupt registers. @@ -985,7 +1081,8 @@ static int i82544EI_init_hw(struct wm_softc *sc) * we resolve the media type. */ sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | - TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | TCTL_RTLC; /*transmitter enable*/ + TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | + TCTL_RTLC /* transmit on late collision */; /* * Set up the receive control register; we actually program @@ -993,14 +1090,31 @@ static int i82544EI_init_hw(struct wm_softc *sc) * address offset type 0. * * Only the i82544 has the ability to strip the incoming - * CRC, so we don't enable that feature. (TODO) + * CRC, so we don't enable that feature. (TODO: |RCTL_SECRC) */ sc->sc_mchash_type = 0; sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | - RCTL_DPF | RCTL_MO(sc->sc_mchash_type); + RCTL_DPF | RCTL_MO(sc->sc_mchash_type)|RCTL_SECRC; - /* (MCLBYTES == 2048) */ - sc->sc_rctl |= RCTL_2k; + if (MCLBYTES == 2048) { + sc->sc_rctl |= RCTL_2k; + } else { + switch(MCLBYTES) { + case 4096: + sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; + break; + case 8192: + sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; + break; + case 16384: + sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; + break; + default: + rtems_panic("wm_init: MCLBYTES %d unsupported", + MCLBYTES); + break; + } + } #ifdef WM_DEBUG printk("RDBAL 0x%x,RDLEN %d, RDT %d\n",CSR_READ(sc,WMREG_RDBAL),CSR_READ(sc,WMREG_RDLEN), CSR_READ(sc,WMREG_RDT)); @@ -1018,6 +1132,24 @@ static int i82544EI_init_hw(struct wm_softc *sc) return(0); } +void BSP_rdTIDV() +{ + printf("Reg TIDV: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV))); +} +void BSP_rdRDTR() +{ + printf("Reg RDTR: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR))); +} + +void BSP_setTIDV(int val) +{ + out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV), val); +} + +void BSP_setRDTR(int val) +{ + out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR), val); +} /* * i82544EI_ifinit: [ifnet interface function] * @@ -1233,6 +1365,7 @@ static int wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint return (0); } +#if 0 /* * wm_acquire_eeprom: * @@ -1264,6 +1397,7 @@ static int wm_acquire_eeprom(struct wm_softc *sc) return (0); } +#endif /* * wm_read_eeprom: @@ -1368,7 +1502,7 @@ static void wm_set_filter(struct wm_softc *sc) mta_reg = WMREG_CORDOVA_MTA; sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); - /* if (ifp->if_flags & IFF_BROADCAST)*/ + if (ifp->if_flags & IFF_BROADCAST) sc->sc_rctl |= RCTL_BAM; if (ifp->if_flags & IFF_PROMISC) { sc->sc_rctl |= RCTL_UPE; @@ -1438,12 +1572,11 @@ static void wm_set_filter(struct wm_softc *sc) static void i82544EI_error(struct wm_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - unsigned long intr_status= sc->intr_errsts[sc->intr_err_ptr1++]; + unsigned long intr_status= sc->if_errsts[sc->if_err_ptr1]; /* read and reset the status; because this is written * by the ISR, we must disable interrupts here */ - sc->intr_err_ptr1 %=INTR_ERR_SIZE; /* Till Straumann */ if (intr_status) { printk("Error %s%d:", ifp->if_name, ifp->if_unit); if (intr_status & ICR_RXSEQ) { @@ -1453,6 +1586,8 @@ static void i82544EI_error(struct wm_softc *sc) } else printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit); + sc->if_errsts[sc->if_err_ptr1]=0; + if ( (++sc->if_err_ptr1) == IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */ } void i82544EI_printStats() @@ -1493,7 +1628,7 @@ static void i82544EI_daemon(void *arg) &events); if (KILL_EVENT & events) break; - if (events & RX_EVENT) i82544EI_rx(sc); + if (events & RX_EVENT) i82544EI_rx(sc); /* in ISR instead */ /* clean up and try sending packets */ do { @@ -1501,6 +1636,7 @@ static void i82544EI_daemon(void *arg) while (sc->txq_free>0) { if (sc->txq_free>TXQ_HiLmt_OFF) { + m=0; IF_DEQUEUE(&ifp->if_snd,m); if (m==0) break; i82544EI_sendpacket(sc, m); @@ -1509,7 +1645,6 @@ static void i82544EI_daemon(void *arg) i82544EI_txq_done(sc); break; } - if (events & RX_EVENT) i82544EI_rx(sc); } /* we leave this loop * - either because there's no free buffer @@ -1517,7 +1652,7 @@ static void i82544EI_daemon(void *arg) * - or there's nothing to send (IF_DEQUEUE * returned 0 */ - } while (m && sc->txq_free); + } while (m); ifp->if_flags &= ~IFF_OACTIVE; @@ -1554,3 +1689,65 @@ static void i82544EI_daemon(void *arg) */ rtems_task_delete(RTEMS_SELF); } + +/* + * wm_gmii_reset: + * + * Reset the PHY. + */ +static void wm_gmii_reset(struct wm_softc *sc) +{ + + CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); + rtems_bsp_delay(20000); + + CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); + rtems_bsp_delay(20000); + +} + +/* + * wm_gmii_mediainit: + * + * Initialize media for use on 1000BASE-T devices. + */ +static void wm_gmii_mediainit(struct wm_softc *sc) +{ + /* struct ifnet *ifp = &sc->arpcom.ac_if;*/ + + /* We have MII. */ + sc->sc_flags |= WM_F_HAS_MII; + + sc->sc_tipg = TIPG_1000T_DFLT; /* 0x602008 */ + + /* + * Let the chip set speed/duplex on its own based on + * signals from the PHY. + * XXXbouyer - I'm not sure this is right for the 80003, + * the em driver only sets CTRL_SLU here - but it seems to work. + */ + sc->sc_ctrl |= CTRL_SLU; + CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); + + wm_gmii_reset(sc); + +#if 0 + /* Initialize our media structures and probe the GMII. */ + sc->sc_mii.mii_ifp = ifp; + + sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; + sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; + sc->sc_mii.mii_statchg = wm_gmii_statchg; + + ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, + wm_gmii_mediastatus); + + mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, + MII_OFFSET_ANY, MIIF_DOPAUSE); + if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { + ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); + ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); + } else + ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); +#endif +} diff --git a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h index d0fd42f1ce..f1615e8cb7 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h @@ -5,6 +5,9 @@ * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * Some are added by Shuchen Kate Feng <feng1@bnl.gov>, + * NSLS, Brookhaven National Laboratory. All rights reserved. + * under the Deaprtment of Energy contract DE-AC02-98CH10886 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -56,7 +59,7 @@ typedef struct wiseman_addr { * The receive descriptor ring must be aligned to a 4K boundary, * and there must be an even multiple of 8 descriptors in the ring. */ -typedef struct wiseman_rxdesc { +typedef volatile struct wiseman_rxdesc { wiseman_addr_t wrx_addr; /* buffer address */ uint16_t wrx_len; /* buffer length */ @@ -103,7 +106,7 @@ typedef struct wiseman_tx_fields { uint8_t wtxu_options; /* options */ uint16_t wtxu_vlan; /* VLAN info */ } __attribute__((__packed__)) wiseman_txfields_t; -typedef struct wiseman_txdesc { +typedef volatile struct wiseman_txdesc { wiseman_addr_t wtx_addr; /* buffer address */ uint32_t wtx_cmdlen; /* command and length */ wiseman_txfields_t wtx_fields; /* fields; see below */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pci_map.c b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pci_map.c index c238e637d0..2bb634add2 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pci_map.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pci_map.c @@ -3,6 +3,7 @@ /*- * Copyright (c) 2004, 2005 Brookhaven National Laboratory * S. Kate Feng <feng1@bnl.gov> + * under the Deaprtment of Energy contract DE-AC02-98CH10886 * * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. * All rights reserved. diff --git a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h index 4a31bbe621..2b8b10d853 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h @@ -4,6 +4,7 @@ * Copyright (c) 1995, 1996, 1999, 2000 * Christopher G. Demetriou. All rights reserved. * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. + * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -30,6 +31,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include <bsp.h> /* * PCI Class and Revision Register; defines type and revision of device. @@ -305,7 +307,7 @@ #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL #define PCI_MAPREG_IO_ADDR(mr) \ - ((mr) & PCI_MAPREG_IO_ADDR_MASK) + ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK) #define PCI_MAPREG_IO_SIZE(mr) \ (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c index 4615464491..712250f545 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c @@ -6,7 +6,8 @@ * Copyright (C) 2001, 2003 Till Straumann <strauman@slac.stanford.edu> * * Copyright (C) 2004 S. Kate Feng, <feng1@bnl.gov> - * wrote it to support the MVME5500 board. + * wrote it to support the MVME5500 board, + * under the Deaprtment of Energy contract DE-AC02-98CH10886. * */ #include <libcpu/io.h> @@ -23,51 +24,53 @@ #define PCI_INVALID_VENDORDEVICEID 0xffffffff #define PCI_MULTI_FUNCTION 0x80 -#define HOSTBRIDGET_ERROR 0xf0000000 unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet) { - unsigned int pcidata, pcidata1; - int PciLocal, busNumber=0; + unsigned long pcidata=0; + unsigned short val; + int PciLocal, busNumber=0, loop; /* On the mvme5500 board, the GT64260B system controller had the MCP * signal pulled up high. Thus, the MCP signal is not used as it is * on other boards such as mvme2307. */ if (enableMCP) return(-1); - for (PciLocal=0; PciLocal<1; PciLocal++ ) { - pci_read_config_dword(busNumber, - 0, - 0, - PCI_COMMAND, - &pcidata); - - if (!quiet) - printk("Before _BSP_clear_hostbridge_errors(): 0x%x, cause 0x%x\n", - pcidata, inl(0x1d58)); - - outl(0,0x1d58); + for (PciLocal=0; PciLocal<2; PciLocal++ ) { + pci_read_config_word(busNumber, + 0, + 0, + PCI_STATUS, + &val); + if ( (val & PCI_STATUS_CLRERR_MASK) && (!quiet)) + printk("Before _BSP_clear_hostbridge_errors(): PCI %d sts was 0x%x\n", + PciLocal, val); + if (!busNumber) + pcidata |= val; + else + pcidata |= (val <<16); - /* Clear the error on the host bridge */ - pcidata1= pcidata; - pcidata1 |= PCI_STATUS_CLRERR_MASK; - pcidata1 |= 0x140; - pci_write_config_dword(busNumber, + for ( loop=0; loop < 10; loop++) { + /* Clear the error on the host bridge */ + pci_write_config_word(busNumber, 0, 0, - PCI_COMMAND, - pcidata1); + PCI_STATUS, + PCI_STATUS_CLRERR_MASK); - pci_read_config_dword(busNumber, + pci_read_config_word(busNumber, 0, 0, - PCI_COMMAND, - &pcidata1); - - if (!quiet) printk("After _BSP_clear_hostbridge_errors(): sts 0x%x\n", - pcidata1); - if (pcidata1 & HOSTBRIDGET_ERROR) printk("BSP_clear_hostbridge_errors(): unable to clear pending hostbridge errors\n"); - busNumber += BSP_MAX_PCI_BUS_ON_PCI0; + PCI_STATUS, + &val); + if ( !(val & PCI_STATUS_CLRERR_MASK)) + break; + else { + if (loop==9) + printk("BSP_clear_hostbridge_errors(): unable to clear pending hostbridge errors\n"); + } + } + busNumber += BSP_MAX_PCI_BUS_ON_PCI0; } - return(pcidata & HOSTBRIDGET_ERROR); + return(pcidata); } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h b/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h index 7548a9304c..c0058928e8 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h @@ -46,7 +46,7 @@ #define PCI_IO_BASE_ADDR PCI_BASE_ADDRESS_5 -#define PCI_STATUS_CLRERR_MASK 0xf9000000 /* <SKF> */ +#define PCI_STATUS_CLRERR_MASK 0xf900 /* <SKF> */ #define PCI_BARE_IntMemEn 0x200 diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c index 729c8a0640..db372e98d6 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c @@ -16,26 +16,28 @@ * pci.c,v 1.2 2002/05/14 17:10:16 joel Exp * * Copyright 2004, Brookhaven National Laboratory and - * Shuchen K. Feng, <feng1@bnl.gov>, 2004 - * - modified and added support for MVME5500 board - * - added 2nd PCI support for the mvme5500/GT64260 PCI bridge - * - added bus support for the expansion of PMCSpan, thanks to - * Peter Dufault (dufault@hda.com) for inputs. + * Shuchen K. Feng, <feng1@bnl.gov>, 2004, 2008 + * + * - to be consistent with the original pci.c written by Eric Valette + * - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100) + * - added bus support for the expansion of PMCSpan as per request by Peter */ #define PCI_MAIN #include <libcpu/io.h> #include <rtems/bspIo.h> /* printk */ +#include <bsp/irq.h> #include <bsp/pci.h> #include <bsp/gtreg.h> #include <bsp/gtpcireg.h> +#include <bsp.h> #include <stdio.h> #include <string.h> #define PCI_DEBUG 0 -#define PCI_PRINT 0 +#define PCI_PRINT 1 /* allow for overriding these definitions */ #ifndef PCI_CONFIG_ADDR @@ -56,17 +58,31 @@ #define PCI_MULTI_FUNCTION 0x80 #define HOSTBRIDGET_ERROR 0xf0000000 -/* define a shortcut */ -#define pci BSP_pci_configuration +#define GT64x60_PCI_CONFIG_ADDR GT64x60_REG_BASE + PCI_CONFIG_ADDR +#define GT64x60_PCI_CONFIG_DATA GT64x60_REG_BASE + PCI_CONFIG_DATA + +#define GT64x60_PCI1_CONFIG_ADDR GT64x60_REG_BASE + PCI1_CONFIG_ADDR +#define GT64x60_PCI1_CONFIG_DATA GT64x60_REG_BASE + PCI1_CONFIG_DATA + +static int numPCIDevs=0; +static DiscoveryChipVersion BSP_sysControllerVersion = 0; +static BSP_VMEchipTypes BSP_VMEinterface = 0; +static pci_config BSP_pci[2]={ + {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), + (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), + 0 /* defined at BSP_pci_configuration */}, + {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR), + (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA), + 0 /* defined at BSP_pci_configuration */} +}; -static int numPCIDevs=0; extern void pci_interface(); /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for * PCI Configuration Address Register */ #define pciConfigPack(bus,dev,func,offset)\ -(((func&7)<<8)|((dev&0x1f )<<11)|(( bus&0xff)<<16)|(offset&0xfc))|0x80000000 +((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80 /* * Bit encode for PCI_CONFIG_HEADER_TYPE register @@ -75,44 +91,36 @@ unsigned char ucMaxPCIBus=0; /* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1. */ -static int direct_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func, +static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset,unsigned char *val) { - volatile unsigned char *config_addr, *config_data; + int n=0; if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { bus-=BSP_MAX_PCI_BUS_ON_PCI0; - config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; - config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; - } - else { - config_addr = pci.pci_config_addr; - config_data = pci.pci_config_data; + n=1; } + *val = 0xff; if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; #if 0 - printk("addr %x, data %x, pack %x \n", config_addr, - config_data,pciConfigPack(bus,dev,func,offset)); + printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr), + BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset)); #endif - outl(pciConfigPack(bus,dev,func,offset),config_addr); - *val = inb(config_data + (offset&3)); + + out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); + *val = in_8(BSP_pci[n].pci_config_data + (offset&3)); return PCIBIOS_SUCCESSFUL; } -static int direct_pci_read_config_word(unsigned char bus, unsigned char dev, +static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev, unsigned char func, unsigned char offset, unsigned short *val) { - volatile unsigned char *config_addr, *config_data; + int n=0; if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { bus-=BSP_MAX_PCI_BUS_ON_PCI0; - config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; - config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; - } - else { - config_addr = (volatile unsigned char*) pci.pci_config_addr; - config_data = (volatile unsigned char*) pci.pci_config_data; + n=1; } *val = 0xffff; @@ -121,123 +129,101 @@ unsigned char func, unsigned char offset, unsigned short *val) printk("addr %x, data %x, pack %x \n", config_addr, config_data,pciConfigPack(bus,dev,func,offset)); #endif - outl(pciConfigPack(bus,dev,func,offset),config_addr); - *val = inw(config_data + (offset&2)); + out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); + *val = in_le16(BSP_pci[n].pci_config_data + (offset&2)); return PCIBIOS_SUCCESSFUL; } -static int direct_pci_read_config_dword(unsigned char bus, unsigned char dev, +static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev, unsigned char func, unsigned char offset, unsigned int *val) { - volatile unsigned char *config_addr, *config_data; + int n=0; if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { bus-=BSP_MAX_PCI_BUS_ON_PCI0; - config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; - config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; - } - else { - config_addr = (volatile unsigned char*) pci.pci_config_addr; - config_data = (volatile unsigned char*) pci.pci_config_data; + n=1; } *val = 0xffffffff; if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; -#if 0 - printk("addr %x, data %x, pack %x \n", config_addr, - pci.pci_config_data,pciConfigPack(bus,dev,func,offset)); -#endif - outl(pciConfigPack(bus,dev,func,offset),config_addr); - *val = inl(config_data); + + out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); + *val = in_le32(BSP_pci[n].pci_config_data); return PCIBIOS_SUCCESSFUL; } -static int direct_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val) +static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val) { - volatile unsigned char *config_addr, *config_data; + int n=0; if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { bus-=BSP_MAX_PCI_BUS_ON_PCI0; - config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; - config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; - } - else { - config_addr = pci.pci_config_addr; - config_data = pci.pci_config_data; + n=1; } if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; -#if 0 - printk("addr %x, data %x, pack %x \n", config_addr, - config_data,pciConfigPack(bus,dev,func,offset)); -#endif - outl(pciConfigPack(bus,dev,func,offset), config_addr); - outb(val, config_data + (offset&3)); + out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); + out_8(BSP_pci[n].pci_config_data + (offset&3), val); return PCIBIOS_SUCCESSFUL; } -static int direct_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val) +static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val) { - volatile unsigned char *config_addr, *config_data; + int n=0; if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { bus-=BSP_MAX_PCI_BUS_ON_PCI0; - config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; - config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; - } - else { - config_addr = (volatile unsigned char*) pci.pci_config_addr; - config_data = (volatile unsigned char*) pci.pci_config_data; + n=1; } if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; -#if 0 - printk("addr %x, data %x, pack %x \n", config_addr, - config_data,pciConfigPack(bus,dev,func,offset)); -#endif - outl(pciConfigPack(bus,dev,func,offset),config_addr); - outw(val, config_data + (offset&3)); + + out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); + out_le16(BSP_pci[n].pci_config_data + (offset&3), val); return PCIBIOS_SUCCESSFUL; } -static int direct_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val) +static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val) { - volatile unsigned char *config_addr, *config_data; + int n=0; if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { bus-=BSP_MAX_PCI_BUS_ON_PCI0; - config_addr = (volatile unsigned char *) PCI1_CONFIG_ADDR; - config_data = (volatile unsigned char *) PCI1_CONFIG_DATA; - } - else { - config_addr = (volatile unsigned char*) pci.pci_config_addr; - config_data = (volatile unsigned char*) pci.pci_config_data; + n=1; } if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; -#if 0 - printk("addr %x, data %x, pack %x \n", config_addr, - config_data,pciConfigPack(bus,dev,func,offset)); -#endif - outl(pciConfigPack(bus,dev,func,offset),config_addr); - outl(val,config_data); + + out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); + out_le32(BSP_pci[n].pci_config_data, val); return PCIBIOS_SUCCESSFUL; } -const pci_config_access_functions pci_direct_functions = { - direct_pci_read_config_byte, - direct_pci_read_config_word, - direct_pci_read_config_dword, - direct_pci_write_config_byte, - direct_pci_write_config_word, - direct_pci_write_config_dword +const pci_config_access_functions pci_indirect_functions = { + indirect_pci_read_config_byte, + indirect_pci_read_config_word, + indirect_pci_read_config_dword, + indirect_pci_write_config_byte, + indirect_pci_write_config_word, + indirect_pci_write_config_dword }; -pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR, - (volatile unsigned char*)PCI_CONFIG_DATA, - &pci_direct_functions}; +pci_config BSP_pci_configuration = { + (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), + (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), + &pci_indirect_functions}; + +DiscoveryChipVersion BSP_getDiscoveryChipVersion() +{ + return(BSP_sysControllerVersion); +} + +BSP_VMEchipTypes BSP_getVMEchipType() +{ + return(BSP_VMEinterface); +} /* * This routine determines the maximum bus number in the system. @@ -248,12 +234,12 @@ pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR, int pci_initialize() { int deviceFound; - unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs; - unsigned int ulHeader; - unsigned int pcidata, ulClass, ulDeviceID; + unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8; + uint32_t ulHeader, ulClass, ulDeviceID; +#if PCI_DEBUG + uint32_t pcidata; +#endif - pci_interface(); - /* * Scan PCI0 and PCI1 buses */ @@ -279,12 +265,36 @@ int pci_initialize() if (!deviceFound) deviceFound=1; switch(ulDeviceID) { case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)): + pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8); + switch(data8) { + case 0x10: + BSP_sysControllerVersion = GT64260A; +#if PCI_PRINT + printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); +#endif + break; + case 0x20: + BSP_sysControllerVersion = GT64260B; +#if PCI_PRINT + printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); +#endif + break; + default: + printk("Undefined revsion of GT64260 chip\n"); + break; + } + break; + case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT64360<<16)): + BSP_sysControllerVersion = MV64360; #if PCI_PRINT - printk("Marvell GT6426xA/B hostbridge detected at bus%d slot%d\n", + printk("Marvell GT64360 (Discovery II) hostbridge detected at bus%d slot%d\n", ucBusNumber,ucSlotNumber); #endif break; case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)): + BSP_VMEinterface = UNIVERSE2; #if PCI_PRINT printk("PLX PCI6154 PCI-PCI bridge detected at bus%d slot%d\n", ucBusNumber,ucSlotNumber); @@ -296,6 +306,13 @@ int pci_initialize() ucBusNumber,ucSlotNumber); #endif break; + case (PCI_VENDOR_ID_TUNDRA+(PCI_DEVICE_ID_TUNDRA_TSI148<<16)): + BSP_VMEinterface = TSI148; +#if PCI_PRINT + printk("TUNDRA Tsi148 PCI/X-VME bridge detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); +#endif + break; case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)): #if PCI_PRINT printk("INTEL 82544EI COPPER network controller detected at bus%d slot%d\n", @@ -303,14 +320,21 @@ int pci_initialize() #endif break; case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)): - #if PCI_PRINT +#if PCI_PRINT printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n", ucBusNumber,ucSlotNumber); #endif break; default : +#if PCI_PRINT printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n", ucBusNumber,ucSlotNumber, ulDeviceID); +#endif + /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */ + pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8); + if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET) pci_write_config_byte(ucBusNumber, + ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8); + break; } @@ -403,34 +427,6 @@ int pci_initialize() #endif } - - pci_read_config_dword(ucBusNumber, - ucSlotNumber, - 0, - PCI_COMMAND, - &pcidata); -#if PCI_DEBUG - printk("MOTLoad command staus 0x%x, ", pcidata); -#endif - /* Clear the error on the host bridge */ - if ( (ucBusNumber==0) && (ucSlotNumber==0)) - pcidata |= PCI_STATUS_CLRERR_MASK; - /* Enable bus,I/O and memory master access. */ - pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY); - pci_write_config_dword(ucBusNumber, - ucSlotNumber, - 0, - PCI_COMMAND, - pcidata); - - pci_read_config_dword(ucBusNumber, - ucSlotNumber, - 0, - PCI_COMMAND, - &pcidata); -#if PCI_DEBUG - printk("Now command/staus 0x%x\n", pcidata); -#endif } if (deviceFound) ucMaxPCIBus++; } /* for (ucBusNumber=0; ucBusNumber<BSP_MAX_PCI_BUS; ... */ @@ -438,6 +434,7 @@ int pci_initialize() printk("number of PCI buses: %d, numPCIDevs %d\n", pci_bus_count(), numPCIDevs); #endif + pci_interface(BSP_sysControllerVersion); return(0); } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.h b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.h index f682d710ea..d9c695a671 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.h @@ -14,8 +14,7 @@ * * pci.h,v 1.2 2002/05/14 17:10:16 joel Exp * - * S. Kate Feng : Added support for Marvell and PLX. 3/5/2004. - + * S. Kate Feng : Added support for Marvell and PLX. 2004, 2007. */ #ifndef RTEMS_PCI_H @@ -23,26 +22,31 @@ #include <rtems/pci.h> -#define PCI_CAPABILITY_LIST_POINTER 0x34 /* <SKF> */ +/************ Beginning of added by Kate Feng **********************/ +#define PCI_CAPABILITY_LIST_POINTER 0x34 /* Device classes and subclasses */ -#define PCI_CLASS_GT6426xAB_BRIDGE_PCI 0x0580 /* <SKF> */ +#define PCI_CLASS_GT6426xAB_BRIDGE_PCI 0x0580 /* * Vendor and card ID's: sort these numerically according to vendor * (and according to card ID within vendor). Send all updates to * <linux-pcisupport@cck.uni-kl.de>. */ -#define PCI_VENDOR_ID_MARVELL 0x11ab /* <SKF> */ -#define PCI_DEVICE_ID_MARVELL_GT6426xAB 0x6430 /* <SKF> */ +#define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_DEVICE_ID_MARVELL_GT6426xAB 0x6430 +#define PCI_DEVICE_ID_MARVELL_GT64360 0x6460 /* Note : The PLX Technology Inc. had the old VENDOR_ID. * See PCI_VENDOR_ID_PLX, PCI_VENDOR_ID_PLX_9050, ..etc. */ -#define PCI_VENDOR_ID_PLX2 0x3388 /* <SKF> */ -#define PCI_DEVICE_ID_PLX2_PCI6154_HB2 0x26 /* <SKF> */ +#define PCI_VENDOR_ID_PLX2 0x3388 +#define PCI_DEVICE_ID_PLX2_PCI6154_HB2 0x26 + +#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148 +#define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008 -#define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008 /* <SKF> */ +/* end of added by Kate Feng */ struct _pin_routes { diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c index f19f9bc69c..729be9bed8 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c @@ -7,10 +7,14 @@ * found in the file LICENSE in this distribution. * * 8/17/2006 : S. Kate Feng - * uses in_le32()/out_le32(), instead of inl()/outl() so that - * it is easier to be ported. + * uses in_le32()/out_le32(), instead of inl()/outl() for compatibility. * + * 11/2008 : Enable "PCI Read Agressive Prefetch", + * "PCI Read Line Agressive Prefetch", and + * "PCI Read Multiple Agressive Prefetch" to improve the + * performance of the PCI based applications (e.g. 1GHz NIC). */ + #include <libcpu/io.h> #include <rtems/bspIo.h> /* printk */ @@ -19,55 +23,29 @@ #include <bsp/gtreg.h> #include <bsp/gtpcireg.h> -#define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg)) -#define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data) - #define PCI_DEBUG 0 -/* Please reference the GT64260B datasheet, for the PCI interface, - * Synchronization Barriers and PCI ordering. - * - * Some PCI devices require Synchronization Barriers or PCI ordering - * for synchronization (only one mechanism allowed. See section 11.1.2). - * To use the former mechanism(default), one needs to call - * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software - * synchronization between the CPU and PCI activities. - * - * To use the PCI-ordering, one can call pciToCpuSync() to trigger - * the PCI-to-CPU sync barrier after the out_xx(). In this mode, - * PCI configuration reads suffer sync barrier latency. Please reference - * the datasheet to explore other options. - * - * Note : If PCI_ORDERING is needed for the PCI0, while disabling the - * deadlock for the PCI0, one should keep the CommDLEn bit enabled - * for the deadlock mechanism so that the 10/100 MB ethernet will - * function correctly. - * - */ -/*#define PCI_ORDERING*/ - -#define EN_SYN_BAR /* take MOTLoad default for enhanced SYN Barrier mode */ - -/*#define PCI_DEADLOCK*/ +#if 0 +#define CPU2PCI_ORDER +#define PCI2CPU_ORDER +#endif -#ifdef PCI_ORDERING -#define PCI_ACCCTLBASEL_VALUE 0x01009000 +/* PCI Read Agressive Prefetch Enable (1<<16 ), + * PCI Read Line Agressive Prefetch Enable( 1<<17), + * PCI Read Multiple Agressive Prefetch Enable (1<<18). + */ +#ifdef PCI2CPU_ORDER +#define PCI_ACCCTLBASEL_VALUE 0x01079000 #else -#define PCI_ACCCTLBASEL_VALUE 0x01001000 +#define PCI_ACCCTLBASEL_VALUE 0x01071000 #endif + #define ConfSBDis 0x10000000 /* 1: disable, 0: enable */ #define IOSBDis 0x20000000 /* 1: disable, 0: enable */ #define ConfIOSBDis 0x30000000 #define CpuPipeline 0x00002000 /* optional, 1:enable, 0:disable */ -#define CPU0_SYNC_TRIGGER 0xD0 /* CPU0 Sync Barrier trigger */ -#define CPU0_SYNC_VIRTUAL 0xC0 /* CPU0 Sync Barrier Virtual */ - -#define CPU1_SYNC_TRIGGER 0xD8 /* CPU1 Sync Barrier trigger */ -#define CPU1_SYNC_VIRTUAL 0xC8 /* CPU1 Sync Barrier Virtual */ - - /* CPU to PCI ordering register */ #define DLOCK_ORDER_REG 0x2D0 /* Deadlock and Ordering register */ #define PCI0OrEn 0x00000001 @@ -86,74 +64,35 @@ #define ADDR_PIPELINE 0x00020000 -void pciAccessInit(); +void pciAccessInit(void); -void pci_interface() +void pci_interface(void) { -#ifdef PCI_DEADLOCK - REG32_WRITE(0x07fff600, CNT_SYNC_REG); +#ifdef CPU2PCI_ORDER + /* MOTLOad deafult : 0x07ff8600 */ + out_le32((volatile unsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600); #endif -#ifdef PCI_ORDERING - /* Let's leave this to be MOTLOad deafult : 0x80070000 - REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/ - /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */ -#endif - - /* asserts SERR upon various detection */ - REG32_WRITE(0x3fffff, 0xc28); - - pciAccessInit(); + /* asserts SERR upon various detection */ + out_le32((volatile unsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff); + pciAccessInit(); } -/* Use MOTLoad default for Writeback Priority and Buffer Depth - */ -void pciAccessInit() + +void pciAccessInit(void) { unsigned int PciLocal, data; for (PciLocal=0; PciLocal < 2; PciLocal++) { - /* MOTLoad combines the two banks of SDRAM into - * one PCI access control because the top = 0x1ff - */ - data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff; + data = in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); +#if 0 + printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data); +#endif data |= PCI_ACCCTLBASEL_VALUE; data &= ~0x300000; - REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)); -#if PCI_DEBUG - printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); + out_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data); +#if 0 + printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)))); #endif - } } -/* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers - * the sync barrier process. The three bits, define which buffers should - * be flushed. - * Bit 0 = PCI0 slave write buffer. - * Bit 1 = PCI1 slave write buffer. - * Bit 2 = SDRAM snoop queue. - */ -void CPU0_PciEnhanceSync(unsigned int syncVal) -{ - REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER); - while (REG32_READ(CPU0_SYNC_VIRTUAL)); -} - -void CPU1_PciEnhanceSync(unsigned int syncVal) -{ - REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER); - while (REG32_READ(CPU1_SYNC_VIRTUAL)); -} - -/* Currently, if PCI_ordering is used for synchronization, configuration - * reads is programmed to be the PCI slave "synchronization barrier" - * cycles. - */ -void pciToCpuSync(int pci_num) -{ - unsigned char data; - unsigned char bus=0; - - if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0; - pci_read_config_byte(bus,0,0,4, &data); -} diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c index c3b677d015..553da37431 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c @@ -7,7 +7,7 @@ * * * Kate Feng <feng1@bnl.gov>, modified it to support the mvme5500 board. - * + * Under the Deaprtment of Energy contract DE-AC02-98CH10886. */ #define PCI_INVALID_VENDORDEVICEID 0xffffffff diff --git a/c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c b/c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c index 1100ddfcd1..d4d2398720 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c @@ -1,3 +1,6 @@ +/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>, + * NSLS,Brookhaven National Laboratory + */ #include <bsp.h> #include <rtems/bspIo.h> #include <libcpu/stackTrace.h> diff --git a/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c index c9d8375359..8008a49f66 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c @@ -17,10 +17,9 @@ * Modified to support the Synergy VGM & Motorola PowerPC boards * (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004, 2005 * - * Modified to support the MVME5500 board. - * Also, the settings of L1, L2, and L3 caches is not necessary here. - * (C) by Brookhaven National Lab., S. Kate Feng <feng1@bnl.gov>, 2003, 2004, 2005 - * + * Modified to support the mvme5500 BSP + * (C) S. Kate Feng,Brookhaven National Lab <feng1@bnl.gov>, 2003, 2004, 2005, 2008 + * * $Id$ */ @@ -42,6 +41,7 @@ #include <libcpu/cpuIdent.h> #include <bsp/vectors.h> #include <bsp/bspException.h> +#include <bsp/VPD.h> #include <rtems/bspIo.h> #include <rtems/sptables.h> @@ -50,8 +50,7 @@ #undef __RTEMS_APPLICATION__ #endif -/* -#define SHOW_MORE_INIT_SETTINGS +/*efine SHOW_MORE_INIT_SETTINGS #define SHOW_LCR1_REGISTER #define SHOW_LCR2_REGISTER #define SHOW_LCR3_REGISTER @@ -74,6 +73,7 @@ extern void BSP_vme_config(void); SPR_RW(SPRG0) SPR_RW(SPRG1) +extern uint32_t probeMemoryEnd(); typedef struct CmdLineRec_ { unsigned long size; @@ -96,6 +96,10 @@ typedef struct CmdLineRec_ { #define MAX_LOADER_ADD_PARM 80 char loaderParam[MAX_LOADER_ADD_PARM]; +BSP_BoardTypes BSP_boardType=0; + +DiscoveryChipVersion BSP_controller_version; + /* * Total memory using RESIDUAL DATA */ @@ -222,6 +226,11 @@ int i=cmdline_end-cmdline_start; cmdline_buf[i]=0; } +BSP_BoardTypes BSP_getBoardType() +{ + return BSP_boardType; +} + /* * bsp_start * @@ -233,6 +242,7 @@ void bsp_start( void ) #ifdef CONF_VPD int i; #endif + int x; unsigned char *stack; unsigned long *r1sp; #ifdef SHOW_LCR1_REGISTER @@ -250,6 +260,8 @@ void bsp_start( void ) ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; Triv121PgTbl pt=0; + ConfVpdRec_t *pVPD = (ConfVpdRec_t *) &ConfVPD_buff[0]; + /* Till Straumann: 4/2005 * Need to map the system registers early, so we can printk... @@ -260,12 +272,11 @@ void bsp_start( void ) */ setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE); - /* Till Straumann: 2004 - * map the PCI 0, 1 Domain I/O space, GT64260B registers - * and the reserved area so that the size is the power of 2. + /* map the PCI 0, 1 Domain I/O space, GT64260B registers, + * Flash Bank 0 and Flash Bank 2. * */ - setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE); + setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE); /* @@ -322,39 +333,33 @@ void bsp_start( void ) */ Cpu_table.exceptions_in_RAM = TRUE; initialize_exceptions(); + + /* <SKF> pci_initialize() before BSP_rtems_irq_mng_init to identify the version of the + * Discovery chip. + */ +#ifdef SHOW_MORE_INIT_SETTINGS + printk("Going to start PCI buses scanning and initialization\n"); +#endif + pci_initialize(); +#ifdef SHOW_MORE_INIT_SETTINGS + printk("Number of PCI buses found is : %d\n", pci_bus_count()); +#endif + + /* + * Initalize RTEMS IRQ system + */ + BSP_rtems_irq_mng_init(0); + /* * Init MMU block address translation to enable hardware * access * More PCI1 memory mapping to be done after BSP_pgtbl_activate. */ printk("-----------------------------------------\n"); - printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version ); + printk("Welcome to %s on MVME5500\n", _RTEMS_version ); printk("-----------------------------------------\n"); -#ifdef TEST_RETURN_TO_PPCBUG - printk("Hit <Enter> to return to PPCBUG monitor\n"); - printk("When Finished hit GO. It should print <Back from monitor>\n"); - debug_getc(); - _return_to_ppcbug(); - printk("Back from monitor\n"); - _return_to_ppcbug(); -#endif /* TEST_RETURN_TO_PPCBUG */ - -#ifdef TEST_RAW_EXCEPTION_CODE - printk("Testing exception handling Part 1\n"); - /* - * Cause a software exception - */ - __asm__ __volatile ("sc"); - /* - * Check we can still catch exceptions and returned coorectly. - */ - printk("Testing exception handling Part 2\n"); - __asm__ __volatile ("sc"); -#endif - - BSP_mem_size = _512M; - /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit of System Status register */ + BSP_mem_size = probeMemoryEnd(); /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */ BSP_bus_frequency = 133333333; BSP_processor_frequency = 1000000000; @@ -401,11 +406,6 @@ void bsp_start( void ) BSP_Configuration.work_space_start = work_space_start; - /* - * Initalize RTEMS IRQ system - */ - BSP_rtems_irq_mng_init(0); - #ifdef SHOW_LCR2_REGISTER l2cr = get_L2CR(); printk("Initial L2CR value = %x\n", l2cr); @@ -429,45 +429,36 @@ void bsp_start( void ) BSP_pgtbl_activate(pt); } + if ( I2Cread_eeprom(0xa8, 0,2, (void *) pVPD, sizeof(ConfVpdRec_t))) + printk("I2Cread_eeprom() error \n"); + else { +#ifdef CONF_VPD + printk("\n"); + for (i=0; i<150; i++) { + printk("%2x ", ConfVPD_buff[i]); + if ((i % 20)==0 ) printk("\n"); + } +#endif + } + /* * PCI 1 domain memory space */ setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE); - -#ifdef SHOW_MORE_INIT_SETTINGS - printk("Going to start PCI buses scanning and initialization\n"); -#endif - pci_initialize(); -#ifdef SHOW_MORE_INIT_SETTINGS - printk("Number of PCI buses found is : %d\n", pci_bus_count()); -#endif - /* Install our own exception handler (needs PCI) */ globalExceptHdl = BSP_exceptionHandler; + +#if 1 /* clear hostbridge errors. MCP signal is not used on the MVME5500 * PCI config space scanning code will trip otherwise :-( */ _BSP_clear_hostbridge_errors(0, 1 /*quiet*/); - - /* Read Configuration Vital Product Data (VPD) */ - if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150)) - printk("I2Cread_eeprom() error \n"); - else { -#ifdef CONF_VPD - printk("\n"); - for (i=0; i<150; i++) { - printk("%2x ", ConfVPD_buff[i]); - if ((i % 20)==0 ) printk("\n"); - } - printk("\n"); #endif - } #ifdef SHOW_MORE_INIT_SETTINGS printk("MSR %x \n", _read_MSR()); printk("Exit from bspstart\n"); #endif - } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c b/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c index 8b14f9923e..379dbadabe 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c @@ -11,6 +11,7 @@ /* Author: Till Straumann, <strauman@slac.stanford.edu>, 4/2002 * Kate Feng <feng1@bnl.gov> ported it to MVME5500, 4/2004 + * */ void diff --git a/c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c b/c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c index d6843a8e4e..ff4706a963 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c @@ -1,3 +1,9 @@ +/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>, + * NSLS,Brookhaven National Laboratory + * + * Ported it from powerpc/shared/console/reboot.c for mvme5500 + * + */ #include <rtems.h> #include <bsp.h> #include <rtems/bspIo.h> @@ -12,5 +18,5 @@ void rtemsReboot() printk("RTEMS terminated; Rebooting ...\n"); /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov> */ - out_8((volatile unsigned char*) (GT64260_DEV1_BASE +2), 0x80); + out_8((volatile unsigned char*) (GT64x60_DEV1_BASE +2), 0x80); } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/vme/vmeconfig.c b/c/src/lib/libbsp/powerpc/mvme5500/vme/vmeconfig.c new file mode 100644 index 0000000000..1094be2a56 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/mvme5500/vme/vmeconfig.c @@ -0,0 +1,132 @@ +/* vmeconfig.c,v 1.1.2.2 2003/03/25 16:46:01 joel Exp */ + +/* Standard VME bridge configuration for PPC boards */ + +/* Copyright Author: Till Straumann <strauman@slac.stanford.edu>, 3/2002 */ + +/* Copyright 2004, Brookhaven National Lab. and S. Kate Feng <feng1@bnl.gov> + * Modified to support the MVME5500, 3/2004 + */ + +#include <bsp.h> +#include <bsp/VME.h> +#include <bsp/VMEConfig.h> +#include <bsp/vmeUniverse.h> +#include <bsp/irq.h> +#include <libcpu/bat.h> + +/* Use a weak alias for the VME configuration. + * This permits individual applications to override + * this routine. + * They may even create an 'empty' + * + * void BSP_vme_config(void) {} + * + * which will avoid linking in the Universe driver + * at all :-). + */ + +void BSP_vme_config(void) __attribute__ (( weak, alias("__BSP_default_vme_config") )); + +/* translate through host bridge and vme master window of vme bridge */ +int +BSP_vme2local_adrs(unsigned long am, unsigned long vmeaddr, unsigned long *plocaladdr) +{ + int rval=vmeUniverseXlateAddr(1,0,am,vmeaddr,plocaladdr); + *plocaladdr+=PCI_MEM_BASE; + return rval; +} + +/* how a CPU address is mapped to the VME bus (if at all) */ +int +BSP_local2vme_adrs(unsigned long am, unsigned long localaddr, unsigned long *pvmeaddr) +{ + return vmeUniverseXlateAddr(0, 0, am,localaddr+PCI_DRAM_OFFSET,pvmeaddr); +} + +int BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg) +{ + return(vmeUniverseInstallISR(vector, handler, arg)); +} + +int +BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg) +{ + return(vmeUniverseRemoveISR(vector, handler, arg)); +} + +/* retrieve the currently installed ISR for a given vector */ +BSP_VME_ISR_t BSP_getVME_isr(unsigned long vector, void **parg) +{ + return(vmeUniverseISRGet(vector, parg)); +} + +int BSP_enableVME_int_lvl(unsigned int level) +{ + return(vmeUniverseIntEnable(level)); +} + +int BSP_disableVME_int_lvl(unsigned int level) +{ + return(vmeUniverseIntDisable(level)); +} + + +void +__BSP_default_vme_config(void) +{ + + vmeUniverseInit(); + vmeUniverseReset(); + + /* setup a PCI0 area to map the VME bus */ + setdbat(0,_VME_A32_WIN0_ON_PCI, _VME_A32_WIN0_ON_PCI, 0x10000000, IO_PAGE); + + /* map VME address ranges */ + vmeUniverseMasterPortCfg( + 0, + VME_AM_EXT_SUP_DATA, + _VME_A32_WIN0_ON_VME, + _VME_A32_WIN0_ON_PCI, + 0x0F000000); + vmeUniverseMasterPortCfg( + 1, + VME_AM_STD_SUP_DATA, + 0x00000000, + _VME_A24_ON_PCI, + 0x00ff0000); + vmeUniverseMasterPortCfg( + 2, + VME_AM_SUP_SHORT_IO, + 0x00000000, + _VME_A16_ON_PCI, + 0x00010000); + +#ifdef _VME_DRAM_OFFSET + /* map our memory to VME */ + vmeUniverseSlavePortCfg( + 0, + VME_AM_EXT_SUP_DATA| VME_AM_IS_MEMORY, + _VME_DRAM_OFFSET, + PCI_DRAM_OFFSET, + BSP_mem_size); + + /* make sure the host bridge PCI master is enabled */ + vmeUniverseWriteReg( + vmeUniverseReadReg(UNIV_REGOFF_PCI_CSR) | UNIV_PCI_CSR_BM, + UNIV_REGOFF_PCI_CSR); +#endif + + /* stdio is not yet initialized; the driver will revert to printk */ + vmeUniverseMasterPortsShow(0); + vmeUniverseSlavePortsShow(0); + + /* install the VME insterrupt manager */ + vmeUniverseInstallIrqMgrAlt(1, + 0, BSP_GPP_IRQ_LOWEST_OFFSET + 12, + 1, BSP_GPP_IRQ_LOWEST_OFFSET + 13, + 2, BSP_GPP_IRQ_LOWEST_OFFSET + 14, + 3, BSP_GPP_IRQ_LOWEST_OFFSET + 15, + -1); + +} |