From 5d957c9c5140742451111cfcf027c295bdf4cd67 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Mon, 6 Aug 2018 09:50:29 +0200
Subject: tester: Add RISC-V support to BSP builder

Update #3433.
---
 tester/rtems/rtems-bsps-riscv.ini | 26 ++++++++++++++++++++++++++
 tester/rtems/rtems-bsps.ini       |  3 +++
 2 files changed, 29 insertions(+)
 create mode 100644 tester/rtems/rtems-bsps-riscv.ini

(limited to 'tester')

diff --git a/tester/rtems/rtems-bsps-riscv.ini b/tester/rtems/rtems-bsps-riscv.ini
new file mode 100644
index 0000000..986d639
--- /dev/null
+++ b/tester/rtems/rtems-bsps-riscv.ini
@@ -0,0 +1,26 @@
+#
+# RTEMS Tools Project (http://www.rtems.org/)
+# Copyright 2018 embedded brains GmbH
+# All rights reserved.
+#
+# This file is part of the RTEMS Tools package in 'rtems-bsp-builder'.
+#
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+#
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+#
+# RISC-V Architecture
+#
+[riscv]
+bsps = rv32iac, rv32i, rv32imac, rv32imafc, rv32imafdc, rv32imafd, rv32im,
+       rv64imac, rv64imac_medany, rv64imafdc, rv64imafd, rv64imafdc_medany,
+       rv64imafd_medany
diff --git a/tester/rtems/rtems-bsps.ini b/tester/rtems/rtems-bsps.ini
index f04f278..bda2b98 100644
--- a/tester/rtems/rtems-bsps.ini
+++ b/tester/rtems/rtems-bsps.ini
@@ -71,6 +71,7 @@ archs = arm,
         moxie,
         or1k,
         powerpc,
+        riscv,
         sh,
         sparc,
         sparc64,
@@ -86,6 +87,7 @@ bsps_mips = ${mips:bsps}
 bsps_moxie = ${moxie:bsps}
 bsps_or1k = ${or1k:bsps}
 bsps_powerpc = ${powerpc:bsps}
+bsps_riscv = ${riscv:bsps}
 bsps_sh = ${sh:bsps}
 bsps_sparc = ${sparc:bsps}
 bsps_sparc64 = ${sparc64:bsps}
@@ -106,6 +108,7 @@ include = rtems-bsps-arm.ini,
           rtems-bsps-moxie.ini,
           rtems-bsps-or1k.ini,
           rtems-bsps-powerpc.ini,
+          rtems-bsps-riscv.ini,
           rtems-bsps-sh.ini,
           rtems-bsps-sparc.ini,
           rtems-bsps-sparc64.ini,
-- 
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