From 4828c19d381af7a1ff64c81ed97362a328d36217 Mon Sep 17 00:00:00 2001 From: Vijay Kumar Banerjee Date: Tue, 5 Feb 2019 22:15:44 +0530 Subject: Coverage : Add coverage support for RISCV --- tester/covoar/TargetFactory.cc | 2 + tester/covoar/Target_riscv.cc | 83 ++++++++++++++++++++++++ tester/covoar/Target_riscv.h | 95 ++++++++++++++++++++++++++++ tester/covoar/wscript | 3 +- tester/rtems/testing/bsps/griscv-sis-cov.ini | 40 ++++++++++++ 5 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 tester/covoar/Target_riscv.cc create mode 100644 tester/covoar/Target_riscv.h create mode 100644 tester/rtems/testing/bsps/griscv-sis-cov.ini (limited to 'tester') diff --git a/tester/covoar/TargetFactory.cc b/tester/covoar/TargetFactory.cc index fc9c30b..12de94d 100644 --- a/tester/covoar/TargetFactory.cc +++ b/tester/covoar/TargetFactory.cc @@ -23,6 +23,7 @@ #include "Target_powerpc.h" #include "Target_lm32.h" #include "Target_sparc.h" +#include "Target_riscv.h" namespace Target { @@ -56,6 +57,7 @@ namespace Target { { "m68k", Target_m68k_Constructor }, { "powerpc", Target_powerpc_Constructor }, { "sparc", Target_sparc_Constructor }, + { "riscv", Target_riscv_Constructor }, { "TBD", NULL }, }; diff --git a/tester/covoar/Target_riscv.cc b/tester/covoar/Target_riscv.cc new file mode 100644 index 0000000..279dc6a --- /dev/null +++ b/tester/covoar/Target_riscv.cc @@ -0,0 +1,83 @@ +/* + * RTEMS Tools Project (http://www.rtems.org/) + * Copyright 2019 Vijay K. Banerjee + * All rights reserved. + * + * This file is part of the RTEMS Tools package in 'rtems-tools'. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*! @file Target_riscv.cc + * @brief Target_riscv Implementation + */ + +#include "Target_riscv.h" +#include +#include +#include +#include + +namespace Target { + + Target_riscv::Target_riscv( std::string targetName ): + TargetBase( targetName ) + { + branchInstructions.push_back("beqz"); + branchInstructions.push_back("bnez"); + branchInstructions.push_back("blez"); + branchInstructions.push_back("bgez"); + branchInstructions.push_back("bltz"); + branchInstructions.push_back("bgt"); + branchInstructions.push_back("bgtz"); + branchInstructions.push_back("ble"); + branchInstructions.push_back("bgtu"); + branchInstructions.push_back("bleu"); + + branchInstructions.sort(); + } + + Target_riscv::~Target_riscv() + { + } + + bool Target_riscv::isNopLine( + const char* const line, + int& size + ) + { + if (!strcmp( &line[strlen(line)-3], "nop")){ + size = 4; + return true; + } + + return false; + } + + TargetBase *Target_riscv_Constructor( + std::string targetName + ) + { + return new Target_riscv( targetName ); + } +} diff --git a/tester/covoar/Target_riscv.h b/tester/covoar/Target_riscv.h new file mode 100644 index 0000000..c1cf7ab --- /dev/null +++ b/tester/covoar/Target_riscv.h @@ -0,0 +1,95 @@ +/* + * RTEMS Tools Project (http://www.rtems.org/) + * Copyright 2019 Vijay K. Banerjee + * All rights reserved. + * + * This file is part of the RTEMS Tools package in 'rtems-tools'. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*! @file Target_riscv.h + * @brief Target_riscv Specification + * + * This file contains the specification of the Target_riscv class. + */ + +#ifndef __TARGET_RISCV_H__ +#define __TARGET_RISCV_H__ + +#include +#include +#include "TargetBase.h" + +namespace Target { + + /*! @class Target_riscv + * + * This is the class for the riscv target. + */ + class Target_riscv: public TargetBase { + + public: + + /*! + * Target_riscv constructor + */ + Target_riscv( std::string targetName ); + + virtual ~Target_riscv(); + + /*! + * This method determines nop instruction. + * + * @param[in] line contains the object dump line to check + * @param[out] size is set to the size in bytes of the nop + * + * @return Returns True if the instruction is nop, False otherwise. + */ + bool isNopLine( + const char* const line, + int& size + ); + + /*! + * This method determines if it's a branch instruction + * + * @param[in] instruction + * + * @return Returns True if the instruction is a branch instruction, False otherwise. + */ + + bool isBranch( + const char* const instruction + ); + + private: + + }; + + TargetBase *Target_riscv_Constructor( + std::string targetName + ); + +} +#endif diff --git a/tester/covoar/wscript b/tester/covoar/wscript index a3730ea..6f722c2 100644 --- a/tester/covoar/wscript +++ b/tester/covoar/wscript @@ -105,7 +105,8 @@ def build(bld): 'Target_lm32.cc', 'Target_m68k.cc', 'Target_powerpc.cc', - 'Target_sparc.cc'], + 'Target_sparc.cc', + 'Target_riscv.cc'], cflags = ['-O2', '-g', '-Wall'], cxxflags = ['-std=c++11', '-O2', '-g', '-Wall'], includes = ['.'] + rtl_includes) diff --git a/tester/rtems/testing/bsps/griscv-sis-cov.ini b/tester/rtems/testing/bsps/griscv-sis-cov.ini new file mode 100644 index 0000000..060bba7 --- /dev/null +++ b/tester/rtems/testing/bsps/griscv-sis-cov.ini @@ -0,0 +1,40 @@ +# +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2019 Vijay K. Banerjee (vijaykumar9597@gmail.com) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# The griscv BSP on sis with coverage +# +[griscv-sis-cov] +bsp = griscv-sis +arch = riscv +tester = %{_rtscripts}/run.cfg +target = riscv-rtems5 +bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis +bsp_run_opts = -nouartrx -r -tlim 300 s -m 4 -cov -- cgit v1.2.3