From e9db9661c98c9e462f47ca5722ef34be13aa2baa Mon Sep 17 00:00:00 2001 From: cvs2git Date: Tue, 15 Sep 2009 05:32:53 +0000 Subject: This commit was manufactured by cvs2svn to create tag 'rtems-4-9-1'. Sprout from rtems-4-9-branch 2008-12-12 15:30:44 UTC Joel Sherrill 'Upgrade to 4.9.1' Cherrypick from rtems-4-9-branch 2009-09-15 05:32:51 UTC cvs2git 'This commit was manufactured by cvs2svn to create branch 'rtems-4-9-branch'.': c/src/lib/libbsp/arm/gba/console/defaultfont.h c/src/lib/libbsp/arm/smdk2410/include/.cvsignore c/src/lib/libbsp/bare/preinstall.am c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore c/src/lib/libbsp/mips/csb350/start/regs.h c/src/lib/libbsp/mips/genmongoosev/start/regs.h c/src/lib/libbsp/mips/hurricane/liblnk/regs.h c/src/lib/libbsp/mips/jmr3904/start/regs.h c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore c/src/lib/libbsp/powerpc/virtex/include/.cvsignore --- c/src/lib/libbsp/arm/gba/console/defaultfont.h | 601 +++++++++++++++++++++ c/src/lib/libbsp/arm/smdk2410/include/.cvsignore | 4 + c/src/lib/libbsp/bare/preinstall.am | 45 ++ .../lib/libbsp/m68k/genmcf548x/include/.cvsignore | 4 + c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore | 4 + c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore | 4 + c/src/lib/libbsp/mips/csb350/start/regs.h | 138 +++++ c/src/lib/libbsp/mips/genmongoosev/start/regs.h | 148 +++++ c/src/lib/libbsp/mips/hurricane/liblnk/regs.h | 137 +++++ c/src/lib/libbsp/mips/jmr3904/start/regs.h | 138 +++++ c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h | 137 +++++ c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h | 137 +++++ .../lib/libbsp/powerpc/mvme3100/include/.cvsignore | 4 + c/src/lib/libbsp/powerpc/virtex/include/.cvsignore | 4 + 14 files changed, 1505 insertions(+) create mode 100644 c/src/lib/libbsp/arm/gba/console/defaultfont.h create mode 100644 c/src/lib/libbsp/arm/smdk2410/include/.cvsignore create mode 100644 c/src/lib/libbsp/bare/preinstall.am create mode 100644 c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore create mode 100644 c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore create mode 100644 c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore create mode 100644 c/src/lib/libbsp/mips/csb350/start/regs.h create mode 100644 c/src/lib/libbsp/mips/genmongoosev/start/regs.h create mode 100644 c/src/lib/libbsp/mips/hurricane/liblnk/regs.h create mode 100644 c/src/lib/libbsp/mips/jmr3904/start/regs.h create mode 100644 c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h create mode 100644 c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h create mode 100644 c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore create mode 100644 c/src/lib/libbsp/powerpc/virtex/include/.cvsignore diff --git a/c/src/lib/libbsp/arm/gba/console/defaultfont.h b/c/src/lib/libbsp/arm/gba/console/defaultfont.h new file mode 100644 index 0000000000..22093f17e1 --- /dev/null +++ b/c/src/lib/libbsp/arm/gba/console/defaultfont.h @@ -0,0 +1,601 @@ +/** + * @file defaultfont.c + * + * This file contains default font definitions. + */ +/* + * RTEMS GBA BSP + * + * Copyright (c) 2004 Markku Puro + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +/** Font array dot value */ +#define X 255 +/** Generate font row data */ +#define GEN_FONT_DATA(a,b,c,d) ( ((d)<<24) | ((c)<<16) | ((b)<<8) | ((a)<<0) ) +/** array for 3x5 font, font screen size is 4x6 */ +static const unsigned long font3x5[256][6] = + { { /* ' ' - ascii:0x20 font:0x00 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '!' - ascii:0x21 font:0x01 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* '"' - ascii:0x22 font:0x02 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '#' - ascii:0x23 font:0x03 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* '$' - ascii:0x24 font:0x04 */ + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* '%' - ascii:0x25 font:0x05 */ + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,0 ) + },{ /* '&' - ascii:0x26 font:0x06 */ + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* ''' - ascii:0x27 font:0x07 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '(' - ascii:0x28 font:0x08 */ + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ) + },{ /* ')' - ascii:0x29 font:0x09 */ + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ) + },{ /* '*' - ascii:0x2A font:0x0A */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '+' - ascii:0x2B font:0x0B */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '´' - ascii:0x2C font:0x0C */ + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '-' - ascii:0x2D font:0x0D */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '.' - ascii:0x2E font:0x0E */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + },{ /* '/' - ascii:0x2F font:0x0F */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( X,0,0,0 ) + },{ /* '0' - ascii:0x30 font:0x10 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '1' - ascii:0x31 font:0x11 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '2' - ascii:0x32 font:0x12 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '3' - ascii:0x33 font:0x13 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '4' - ascii:0x34 font:0x14 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,X ) + },{ /* '5' - ascii:0x35 font:0x15 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '6' - ascii:0x36 font:0x16 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '7' - ascii:0x37 font:0x17 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* '8' - ascii:0x38 font:0x18 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '9' - ascii:0x39 font:0x19 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* ':' - ascii:0x3A font:0x1A */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + },{ /* ';' - ascii:0x3B font:0x1B */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + },{ /* '<' - ascii:0x3C font:0x1C */ + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ) + },{ /* '=' - ascii:0x3D font:0x1D */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '>' - ascii:0x3E font:0x1E */ + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ) + },{ /* '?' - ascii:0x3F font:0x1F */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* '@' - ascii:0x40 font:0x20 */ + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* 'A' - ascii:0x41 font:0x21 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'B' - ascii:0x42 font:0x22 */ + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ) + },{ /* 'C' - ascii:0x43 font:0x23 */ + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* 'D' - ascii:0x44 font:0x24 */ + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + },{ /* 'E' - ascii:0x45 font:0x25 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* 'F' - ascii:0x46 font:0x26 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + },{ /* 'G' - ascii:0x47 font:0x27 */ + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* 'H' - ascii:0x48 font:0x28 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'I' - ascii:0x49 font:0x29 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* 'J' - ascii:0x4A font:0x2A */ + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* 'K' - ascii:0x4B font:0x2B */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'L' - ascii:0x4C font:0x2C */ + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* 'M' - ascii:0x4D font:0x2D */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'N' - ascii:0x4E font:0x2E */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'O' - ascii:0x4F font:0x2F */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* 'P' - ascii:0x50 font:0x30 */ + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + },{ /* 'Q' - ascii:0x51 font:0x31 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* 'R' - ascii:0x52 font:0x33 */ + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'S' - ascii:0x53 font:0x33 */ + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,X,0 ) + },{ /* 'T' - ascii:0x54 font:0x34 */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + },{ /* 'U' - ascii:0x55 font:0x35 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* 'V' - ascii:0x56 font:0x36 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + },{ /* 'W' - ascii:0x57 font:0x37 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + },{ /* 'X' - ascii:0x58 font:0x38 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'Y' - ascii:0x59 font:0x39 */ + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + },{ /* 'Z' - ascii:0x5A font:0x3A */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '[' - ascii:0x5B font:0x3B */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '\' - ascii:0x5C font:0x3C */ + GEN_FONT_DATA( X,0,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* ']' - ascii:0x5D font:0x3D */ + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '^' - ascii:0x5E font:0x3E */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '_' - ascii:0x5F font:0x3F */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '´' - ascii:0x60 font:0x30 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* 'a' - ascii:0x31 font:0x31 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* 'b' - ascii:0x62 font:0x32 */ + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ) + },{ /* 'c' - ascii:0x63 font:0x33 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* 'd' - ascii:0x64 font:0x34 */ + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,X ), + },{ /* 'e' - ascii:0x65 font:0x35 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* 'f' - ascii:0x66 font:0x36 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,0 ), + },{ /* 'g' - ascii:0x67 font:0x37 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,X,0 ) + },{ /* 'h' - ascii:0x68 font:0x38 */ + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'i' - ascii:0x69 font:0x39 */ + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* 'j' - ascii:0x6A font:0x3A */ + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* 'k' - ascii:0x6B font:0x3B */ + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'l' - ascii:0x6C font:0x3C */ + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* 'm' - ascii:0x6D font:0x3D */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'n' - ascii:0x6E font:0x3E */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'o' - ascii:0x6F font:0x6F */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ) + },{ /* 'p' - ascii:0x70 font:0x40 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + },{ /* 'q' - ascii:0x71 font:0x41 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,0,0,X ) + },{ /* 'r' - ascii:0x72 font:0x43 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ) + },{ /* 's' - ascii:0x73 font:0x43 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,X,X,0 ) + },{ /* 't' - ascii:0x74 font:0x44 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,X ), + },{ /* 'u' - ascii:0x75 font:0x45 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* 'v' - ascii:0x76 font:0x46 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + },{ /* 'w' - ascii:0x77 font:0x47 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,X,0,X ), + },{ /* 'x' - ascii:0x78 font:0x48 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,X ) + },{ /* 'y' - ascii:0x79 font:0x49 */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + },{ /* 'z' - ascii:0x7A font:0x4A */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,X,X ) + },{ /* '{' - ascii:0x7B font:0x4B */ + GEN_FONT_DATA( 0,0,X,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,X,X ) + },{ /* '\' - ascii:0x7C font:0x4C */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* '}' - ascii:0x7D font:0x4D */ + GEN_FONT_DATA( 0,X,X,0 ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,X,0 ), + GEN_FONT_DATA( 0,X,X,0 ) + },{ /* '~' - ascii:0x7E font:0x4E */ + GEN_FONT_DATA( 0,0,0,0 ), + GEN_FONT_DATA( 0,X,0,0 ), + GEN_FONT_DATA( 0,X,X,X ), + GEN_FONT_DATA( 0,0,0,X ), + GEN_FONT_DATA( 0,0,0,0 ) + },{ /* DEL - ascii:0x7F font:0x4F */ + GEN_FONT_DATA( X,X,X,X ), + GEN_FONT_DATA( X,X,X,X ), + GEN_FONT_DATA( X,X,X,X ), + GEN_FONT_DATA( X,X,X,X ), + GEN_FONT_DATA( X,X,X,X ) + } + }; diff --git a/c/src/lib/libbsp/arm/smdk2410/include/.cvsignore b/c/src/lib/libbsp/arm/smdk2410/include/.cvsignore new file mode 100644 index 0000000000..a83132db41 --- /dev/null +++ b/c/src/lib/libbsp/arm/smdk2410/include/.cvsignore @@ -0,0 +1,4 @@ +stamp-h +stamp-h.in +bspopts.h +bspopts.h.in diff --git a/c/src/lib/libbsp/bare/preinstall.am b/c/src/lib/libbsp/bare/preinstall.am new file mode 100644 index 0000000000..d2bc0e46ad --- /dev/null +++ b/c/src/lib/libbsp/bare/preinstall.am @@ -0,0 +1,45 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_INCLUDE)/coverhd.h: ../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + diff --git a/c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore b/c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore new file mode 100644 index 0000000000..a83132db41 --- /dev/null +++ b/c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore @@ -0,0 +1,4 @@ +stamp-h +stamp-h.in +bspopts.h +bspopts.h.in diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore b/c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore new file mode 100644 index 0000000000..a83132db41 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore @@ -0,0 +1,4 @@ +stamp-h +stamp-h.in +bspopts.h +bspopts.h.in diff --git a/c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore b/c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore new file mode 100644 index 0000000000..a83132db41 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore @@ -0,0 +1,4 @@ +stamp-h +stamp-h.in +bspopts.h +bspopts.h.in diff --git a/c/src/lib/libbsp/mips/csb350/start/regs.h b/c/src/lib/libbsp/mips/csb350/start/regs.h new file mode 100644 index 0000000000..07ab06ad92 --- /dev/null +++ b/c/src/lib/libbsp/mips/csb350/start/regs.h @@ -0,0 +1,138 @@ +/* + * regs.S -- standard MIPS register names from + * newlib-1.8.2/libgloss/mips and adapted. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* Standard MIPS register names: */ +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel private register 0 */ +#define k1 $27 /* kernel private register 1 */ +#define gp $28 /* global data pointer */ +#define sp $29 /* stack-pointer */ +#define fp $30 /* frame-pointer */ +#define ra $31 /* return address */ +#define pc $pc /* pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +/* Useful memory constants: */ +#define K0BASE 0x80000000 +#ifndef __mips64 +#define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/* Standard Co-Processor 0 register numbers: */ +#define C0_COUNT $9 /* Count Register */ +#define C0_SR $12 /* Status Register */ +#define C0_CAUSE $13 /* last exception description */ +#define C0_EPC $14 /* Exception error address */ +#define C0_CONFIG $16 /* CPU configuration */ + +/* Standard Status Register bitmasks: */ +#define SR_CU1 0x20000000 /* Mark CP1 as usable */ +#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 /* Controls location of exception vectors */ +#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ + +#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ +#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 /* User extended addressing enabled */ + +/* Standard (R4000) cache operations. Taken from "MIPS R4000 + Microprocessor User's Manual" 2nd edition: */ + +#define CACHE_I (0) /* primary instruction */ +#define CACHE_D (1) /* primary data */ +#define CACHE_SI (2) /* secondary instruction */ +#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) /* CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/* Individual cache operations: */ +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + +/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/mips/genmongoosev/start/regs.h b/c/src/lib/libbsp/mips/genmongoosev/start/regs.h new file mode 100644 index 0000000000..e63544f738 --- /dev/null +++ b/c/src/lib/libbsp/mips/genmongoosev/start/regs.h @@ -0,0 +1,148 @@ +/* + * regs.S -- standard MIPS register names from + * newlib-1.8.2/libgloss/mips and adapted. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* Standard MIPS register names: */ +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel private register 0 */ +#define k1 $27 /* kernel private register 1 */ +#define gp $28 /* global data pointer */ +#define sp $29 /* stack-pointer */ +#define fp $30 /* frame-pointer */ +#define ra $31 /* return address */ +#define pc $pc /* pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +#define WATCHDOG 0xBE000000 + +/* Useful memory constants: */ +#define K0BASE 0x80000000 +#ifndef __mips64 + #define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/* Standard Co-Processor 0 register numbers: */ +#define C0_DCIC $7 /* debug & cache invalidate control */ +#define C0_COUNT $9 /* Count Register */ +#define C0_SR $12 /* Status Register */ +#define C0_CAUSE $13 /* last exception description */ +#define C0_EPC $14 /* Exception error address */ +#define C0_CONFIG $16 /* CPU configuration */ + +/* Standard Status Register bitmasks: */ +#define SR_CU0 0x10000000 +#define SR_CU1 0x20000000 /* Mark CP1 as usable */ +#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 /* Controls location of exception vectors */ +#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ + +/* defined differently for Mongoose5- we don't use these anymore */ +#if UNUSED +#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ +#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 /* User extended addressing enabled */ +#endif + +/* R3000 */ +#define SR_ISC 0x00010000 /* Isolate data cache */ + +/* Standard (R4000) cache operations. Taken from "MIPS R4000 + Microprocessor User's Manual" 2nd edition: */ + +#define CACHE_I (0) /* primary instruction */ +#define CACHE_D (1) /* primary data */ +#define CACHE_SI (2) /* secondary instruction */ +#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) /* CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/* Individual cache operations: */ +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + +/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/mips/hurricane/liblnk/regs.h b/c/src/lib/libbsp/mips/hurricane/liblnk/regs.h new file mode 100644 index 0000000000..1befa8dc79 --- /dev/null +++ b/c/src/lib/libbsp/mips/hurricane/liblnk/regs.h @@ -0,0 +1,137 @@ +/* + * regs.S -- standard MIPS register names. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* Standard MIPS register names: */ +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel private register 0 */ +#define k1 $27 /* kernel private register 1 */ +#define gp $28 /* global data pointer */ +#define sp $29 /* stack-pointer */ +#define fp $30 /* frame-pointer */ +#define ra $31 /* return address */ +#define pc $pc /* pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +/* Useful memory constants: */ +#define K0BASE 0x80000000 +#ifndef __mips64 +#define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/* Standard Co-Processor 0 register numbers: */ +#define C0_COUNT $9 /* Count Register */ +#define C0_SR $12 /* Status Register */ +#define C0_CAUSE $13 /* last exception description */ +#define C0_EPC $14 /* Exception error address */ +#define C0_CONFIG $16 /* CPU configuration */ + +/* Standard Status Register bitmasks: */ +#define SR_CU1 0x20000000 /* Mark CP1 as usable */ +#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 /* Controls location of exception vectors */ +#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ + +#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ +#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 /* User extended addressing enabled */ + +/* Standard (R4000) cache operations. Taken from "MIPS R4000 + Microprocessor User's Manual" 2nd edition: */ + +#define CACHE_I (0) /* primary instruction */ +#define CACHE_D (1) /* primary data */ +#define CACHE_SI (2) /* secondary instruction */ +#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) /* CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/* Individual cache operations: */ +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + +/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/mips/jmr3904/start/regs.h b/c/src/lib/libbsp/mips/jmr3904/start/regs.h new file mode 100644 index 0000000000..07ab06ad92 --- /dev/null +++ b/c/src/lib/libbsp/mips/jmr3904/start/regs.h @@ -0,0 +1,138 @@ +/* + * regs.S -- standard MIPS register names from + * newlib-1.8.2/libgloss/mips and adapted. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* Standard MIPS register names: */ +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel private register 0 */ +#define k1 $27 /* kernel private register 1 */ +#define gp $28 /* global data pointer */ +#define sp $29 /* stack-pointer */ +#define fp $30 /* frame-pointer */ +#define ra $31 /* return address */ +#define pc $pc /* pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +/* Useful memory constants: */ +#define K0BASE 0x80000000 +#ifndef __mips64 +#define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/* Standard Co-Processor 0 register numbers: */ +#define C0_COUNT $9 /* Count Register */ +#define C0_SR $12 /* Status Register */ +#define C0_CAUSE $13 /* last exception description */ +#define C0_EPC $14 /* Exception error address */ +#define C0_CONFIG $16 /* CPU configuration */ + +/* Standard Status Register bitmasks: */ +#define SR_CU1 0x20000000 /* Mark CP1 as usable */ +#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 /* Controls location of exception vectors */ +#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ + +#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ +#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 /* User extended addressing enabled */ + +/* Standard (R4000) cache operations. Taken from "MIPS R4000 + Microprocessor User's Manual" 2nd edition: */ + +#define CACHE_I (0) /* primary instruction */ +#define CACHE_D (1) /* primary data */ +#define CACHE_SI (2) /* secondary instruction */ +#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) /* CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/* Individual cache operations: */ +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + +/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h b/c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h new file mode 100644 index 0000000000..1befa8dc79 --- /dev/null +++ b/c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h @@ -0,0 +1,137 @@ +/* + * regs.S -- standard MIPS register names. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* Standard MIPS register names: */ +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel private register 0 */ +#define k1 $27 /* kernel private register 1 */ +#define gp $28 /* global data pointer */ +#define sp $29 /* stack-pointer */ +#define fp $30 /* frame-pointer */ +#define ra $31 /* return address */ +#define pc $pc /* pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +/* Useful memory constants: */ +#define K0BASE 0x80000000 +#ifndef __mips64 +#define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/* Standard Co-Processor 0 register numbers: */ +#define C0_COUNT $9 /* Count Register */ +#define C0_SR $12 /* Status Register */ +#define C0_CAUSE $13 /* last exception description */ +#define C0_EPC $14 /* Exception error address */ +#define C0_CONFIG $16 /* CPU configuration */ + +/* Standard Status Register bitmasks: */ +#define SR_CU1 0x20000000 /* Mark CP1 as usable */ +#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 /* Controls location of exception vectors */ +#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ + +#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ +#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 /* User extended addressing enabled */ + +/* Standard (R4000) cache operations. Taken from "MIPS R4000 + Microprocessor User's Manual" 2nd edition: */ + +#define CACHE_I (0) /* primary instruction */ +#define CACHE_D (1) /* primary data */ +#define CACHE_SI (2) /* secondary instruction */ +#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) /* CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/* Individual cache operations: */ +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + +/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h b/c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h new file mode 100644 index 0000000000..1befa8dc79 --- /dev/null +++ b/c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h @@ -0,0 +1,137 @@ +/* + * regs.S -- standard MIPS register names. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* Standard MIPS register names: */ +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel private register 0 */ +#define k1 $27 /* kernel private register 1 */ +#define gp $28 /* global data pointer */ +#define sp $29 /* stack-pointer */ +#define fp $30 /* frame-pointer */ +#define ra $31 /* return address */ +#define pc $pc /* pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +/* Useful memory constants: */ +#define K0BASE 0x80000000 +#ifndef __mips64 +#define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/* Standard Co-Processor 0 register numbers: */ +#define C0_COUNT $9 /* Count Register */ +#define C0_SR $12 /* Status Register */ +#define C0_CAUSE $13 /* last exception description */ +#define C0_EPC $14 /* Exception error address */ +#define C0_CONFIG $16 /* CPU configuration */ + +/* Standard Status Register bitmasks: */ +#define SR_CU1 0x20000000 /* Mark CP1 as usable */ +#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 /* Controls location of exception vectors */ +#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ + +#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ +#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 /* User extended addressing enabled */ + +/* Standard (R4000) cache operations. Taken from "MIPS R4000 + Microprocessor User's Manual" 2nd edition: */ + +#define CACHE_I (0) /* primary instruction */ +#define CACHE_D (1) /* primary data */ +#define CACHE_SI (2) /* secondary instruction */ +#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) /* CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/* Individual cache operations: */ +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + +/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore b/c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore new file mode 100644 index 0000000000..a83132db41 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore @@ -0,0 +1,4 @@ +stamp-h +stamp-h.in +bspopts.h +bspopts.h.in diff --git a/c/src/lib/libbsp/powerpc/virtex/include/.cvsignore b/c/src/lib/libbsp/powerpc/virtex/include/.cvsignore new file mode 100644 index 0000000000..a83132db41 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/virtex/include/.cvsignore @@ -0,0 +1,4 @@ +stamp-h +stamp-h.in +bspopts.h +bspopts.h.in -- cgit v1.2.3