From 8fb685b7a35532da5c37e53cfdaa2eda6c45684c Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 5 Jun 2014 08:41:56 +0200 Subject: bsp/altera-cyclone-v: Simplify start hooks Use arm_a9mpcore_start_hook_0(). The L2 cache is now disabled. --- .../arm/altera-cyclone-v/startup/bspstarthooks.c | 145 ++++----------------- 1 file changed, 25 insertions(+), 120 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c index 213d243af4..d913c8e0c6 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -20,27 +20,16 @@ #include #include #include -#include "socal/socal.h" -#include "socal/alt_sdr.h" -#include "socal/hps.h" -#include "../include/arm-cache-l1.h" - -#ifdef RTEMS_SMP - #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_SHAREABLE -#else - #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_CACHED -#endif +#include +#include +#include /* 1 MB reset default value for address filtering start */ #define BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 -#ifndef BSPSTARTHOOKS_MIN -#define BSPSTARTHOOKS_MIN( a, b ) ( ( a ) < ( b ) ? ( a ) : ( b ) ) -#endif - -LINKER_SYMBOL( bsp_section_nocache_size ); -LINKER_SYMBOL( bsp_section_nocache_end ); -LINKER_SYMBOL( bsp_section_nocache_begin ); +LINKER_SYMBOL(bsp_section_nocache_size); +LINKER_SYMBOL(bsp_section_nocache_end); +LINKER_SYMBOL(bsp_section_nocache_begin); BSP_START_DATA_SECTION static const arm_cp15_start_section_config altcycv_mmu_config_table[] = { @@ -56,111 +45,27 @@ BSP_START_DATA_SECTION static const arm_cp15_start_section_config } }; -BSP_START_TEXT_SECTION static void setup_mmu_and_cache( const uint32_t CPU_ID ) +BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) { - uint32_t ctrl = arm_cp15_get_control(); - const uint32_t CORES = BSPSTARTHOOKS_MIN( - (uintptr_t) bsp_processor_count, - rtems_configuration_get_maximum_processors() ); - - /* We expect the L1 caches and program flow prediction to be off */ - assert( ( ctrl & ARM_CP15_CTRL_I ) == 0 ); - assert( ( ctrl & ARM_CP15_CTRL_C ) == 0 ); - assert( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ); - - ctrl = arm_cp15_start_setup_mmu_and_cache( - ARM_CP15_CTRL_A | ARM_CP15_CTRL_M, - ARM_CP15_CTRL_AFE - ); - - if( CPU_ID == 0 ) { - arm_cp15_start_setup_translation_table( - (uint32_t *) bsp_translation_table_base, - ARM_MMU_DEFAULT_CLIENT_DOMAIN, - &altcycv_mmu_config_table[0], - RTEMS_ARRAY_SIZE( altcycv_mmu_config_table ) - ); - } else { - /* FIXME: Sharing the translation table between processors is brittle */ - arm_cp15_set_translation_table_base((uint32_t *) bsp_translation_table_base); - } - - /* Enable MMU */ - ctrl |= ARM_CP15_CTRL_M; - - arm_cp15_set_control( ctrl ); - - if( CPU_ID == (CORES - 1) ) { - /* Enable all cache levels for the last core */ - rtems_cache_enable_instruction(); - rtems_cache_enable_data(); - } else { - /* Enable only L1 cache */ - arm_cache_l1_enable_data(); - arm_cache_l1_enable_instruction(); - } - - /* Enable flow control prediction aka. branch prediction */ - -/* TODO: With the current network stack 06-Feb2014 in_checksum() - * becomes a severe performance bottle neck with branch prediction enabled - ctrl |= ARM_CP15_CTRL_Z; - arm_cp15_set_control(ctrl);*/ + arm_cp15_instruction_cache_invalidate(); + arm_cp15_data_cache_invalidate_all_levels(); + arm_a9mpcore_start_hook_0(); } -BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) +BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void) { - uint32_t ctrl; - volatile a9mpcore_scu *scu = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE; - uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); - const uint32_t CORES = BSPSTARTHOOKS_MIN( - (uintptr_t) bsp_processor_count, - rtems_configuration_get_maximum_processors() ); - - assert( cpu_id < CORES ); - - if( cpu_id < CORES ) { - if( cpu_id == 0 ) { - ctrl = arm_cp15_mmu_disable( 32 ); - - ctrl &= ~( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_Z ); - arm_cp15_set_control( ctrl ); - - /* Enable Snoop Control Unit (SCU) */ - arm_a9mpcore_start_scu_enable( scu ); - } - -#ifdef RTEMS_SMP - /* Enable cache coherency support for this processor */ - uint32_t actlr = arm_cp15_get_auxiliary_control(); - actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; - arm_cp15_set_auxiliary_control(actlr); -#endif - - if (cpu_id == 0) { - arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xF); - } - - setup_mmu_and_cache( cpu_id ); - -#ifdef RTEMS_SMP - if (cpu_id != 0) { - arm_a9mpcore_start_set_vector_base(); - - arm_gic_irq_initialize_secondary_cpu(); - - arm_cp15_set_domain_access_control( - ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT) - ); - _SMP_Start_multitasking_on_secondary_processor(); - } -#endif - } else { - /* FIXME: Shutdown processor */ - while (1) { - __asm__ volatile ("wfi"); - } - } + uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache( + ARM_CP15_CTRL_A | ARM_CP15_CTRL_M, + ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z + ); + + arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( + ctrl, + (uint32_t *) bsp_translation_table_base, + ARM_MMU_DEFAULT_CLIENT_DOMAIN, + &altcycv_mmu_config_table[0], + RTEMS_ARRAY_SIZE(altcycv_mmu_config_table) + ); } BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) @@ -198,6 +103,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) arm_a9mpcore_start_hook_1(); bsp_start_copy_sections(); - + setup_mmu_and_cache(); bsp_start_clear_bss(); } -- cgit v1.2.3