From 1468d70f7938476f4eba65f7e4d322550ae1a7c9 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 5 Jun 2014 10:03:55 +0200 Subject: bsp/altera-cyclone-v: Enable unified L2 cache --- c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c | 9 ++++++++- c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c | 4 ++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c index 3b894b460f..591e1cd2e8 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c @@ -55,7 +55,11 @@ bool _CPU_SMP_Start_processor(uint32_t cpu_index) ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK ); - started = true; + /* + * Wait for secondary processor to complete its basic initialization so + * that we can enable the unified L2 cache. + */ + started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0); } else { started = false; } @@ -76,6 +80,9 @@ void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) NULL ); assert(sc == RTEMS_SUCCESSFUL); + + /* Enable unified L2 cache */ + rtems_cache_enable_data(); } } diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c index d913c8e0c6..e543ea27d1 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c @@ -104,5 +104,9 @@ BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) arm_a9mpcore_start_hook_1(); bsp_start_copy_sections(); setup_mmu_and_cache(); +#ifndef RTEMS_SMP + /* Enable unified L2 cache */ + rtems_cache_enable_data(); +#endif bsp_start_clear_bss(); } -- cgit v1.2.3