diff options
Diffstat (limited to 'cpukit/libpci/pci')
| -rw-r--r-- | cpukit/libpci/pci/access.h | 315 | ||||
| -rw-r--r-- | cpukit/libpci/pci/cfg.h | 237 | ||||
| -rw-r--r-- | cpukit/libpci/pci/cfg_auto.h | 51 | ||||
| -rw-r--r-- | cpukit/libpci/pci/cfg_peripheral.h | 12 | ||||
| -rw-r--r-- | cpukit/libpci/pci/cfg_read.h | 14 | ||||
| -rw-r--r-- | cpukit/libpci/pci/cfg_static.h | 14 | ||||
| -rw-r--r-- | cpukit/libpci/pci/ids.h | 802 | ||||
| -rw-r--r-- | cpukit/libpci/pci/ids_extra.h | 19 | ||||
| -rw-r--r-- | cpukit/libpci/pci/irq.h | 98 |
9 files changed, 1562 insertions, 0 deletions
diff --git a/cpukit/libpci/pci/access.h b/cpukit/libpci/pci/access.h new file mode 100644 index 0000000000..a3f351f60b --- /dev/null +++ b/cpukit/libpci/pci/access.h @@ -0,0 +1,315 @@ +/* Routines to access PCI memory/configuration space and other PCI related + * functions the PCI Library provides. + */ + +#ifndef __PCI_ACCESS_H__ +#define __PCI_ACCESS_H__ + +#include <stdint.h> +#include <libcpu/byteorder.h> +#include <pci.h> + +/* Let BSP configure load/store from PCI */ +#include <bsp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Identification of a PCI configuration space device (16-bit) */ +typedef uint16_t pci_dev_t; +/* Create a PCI Configuration Space ID */ +#define PCI_DEV(bus, slot, func) (((bus)<<8) | ((slot)<<3) | (func)) +/* Get Bus of a PCI Configuration Space ID */ +#define PCI_DEV_BUS(dev) (((dev) >> 8) & 0xff) +/* Get Slot/Device of a PCI Configuration Space ID */ +#define PCI_DEV_SLOT(dev) (((dev) >> 3) & 0x1f) +/* Get Function of a PCI Configuration Space ID */ +#define PCI_DEV_FUNC(dev) ((dev) & 0x7) +/* Get Device and Function of a PCI Configuration Space ID */ +#define PCI_DEV_DEVFUNC(dev) ((dev) & 0xff) +/* Expand Device into argument lists */ +#define PCI_DEV_EXPAND(dev) PCI_DEV_BUS((dev)), PCI_DEV_SLOT((dev)), PCI_DEV_FUNC((dev)) + +/* Configuration Space Read/Write Operations */ +struct pci_cfg_ops { + /* Configuration Space Access and Setup Routines */ + int (*read8)(pci_dev_t dev, int ofs, uint8_t *data); + int (*read16)(pci_dev_t dev, int ofs, uint16_t *data); + int (*read32)(pci_dev_t dev, int ofs, uint32_t *data); + int (*write8)(pci_dev_t dev, int ofs, uint8_t data); + int (*write16)(pci_dev_t dev, int ofs, uint16_t data); + int (*write32)(pci_dev_t dev, int ofs, uint32_t data); +}; + +/* Read a register over PCI I/O Space, and swap it if necessary (due to + * PCI endianness) + */ +struct pci_io_ops { + uint8_t (*read8)(uint8_t *adr); + uint16_t(*read16)(uint16_t *adr); + uint32_t (*read32)(uint32_t *adr); + void (*write8)(uint8_t *adr, uint8_t data); + void (*write16)(uint16_t *adr, uint16_t data); + void (*write32)(uint32_t *adr, uint32_t data); +}; + +/* Read a register over PCI Memory Space (non-prefetchable memory), and + * swap it if necessary (due to PCI endianness) + */ +struct pci_memreg_ops { + uint8_t (*ld8)(uint8_t *adr); + void (*st8)(uint8_t *adr, uint8_t data); + + uint16_t(*ld_le16)(uint16_t *adr); + void (*st_le16)(uint16_t *adr, uint16_t data); + uint16_t(*ld_be16)(uint16_t *adr); + void (*st_be16)(uint16_t *adr, uint16_t data); + + uint32_t (*ld_le32)(uint32_t *adr); + void (*st_le32)(uint32_t *adr, uint32_t data); + uint32_t (*ld_be32)(uint32_t *adr); + void (*st_be32)(uint32_t *adr, uint32_t data); +}; + +typedef uint8_t (*pci_ld8_t)(uint8_t *adr); +typedef void (*pci_st8_t)(uint8_t *adr, uint8_t data); +typedef uint16_t(pci_ld16_t)(uint16_t *adr); +typedef void (*pci_st16_t)(uint16_t *adr, uint16_t data); +typedef uint32_t (*pci_ld32_t)(uint32_t *adr); +typedef void (*pci_st32_t)(uint32_t *adr, uint32_t data); + +struct pci_access_drv { + /* Configuration */ + struct pci_cfg_ops cfg; + + /* I/O Access operations */ + struct pci_io_ops io; + + /* Registers over Memory Access operations. Note that these funcs + * are only for code that need to be compatible with both Big-Endian + * and Little-Endian PCI bus or for some other reason need function + * pointers to access functions. Normally drivers use the inline + * functions for Registers-over-Memory access to avoid extra function + * call. + */ + struct pci_memreg_ops *memreg; + + /* Translate from PCI address to CPU address (dir=0). Translate + * CPU address to PCI address (dir!=0). The address will can be + * used to perform I/O access or memory access by CPU or PCI DMA + * peripheral. + * + * address In/Out. CPU address or PCI address. + * type Access type. 1=I/O, 2=MEMIO, 3=MEM + * dir Translate direction. 0=PCI-to-CPU, 0!=CPU-to-PCI, + * + * Return Value + * 0 = Success + * -1 = Requested Address not mapped into other address space + * i.e. not accessible + */ + int (*translate)(uint32_t *address, int type, int dir); +}; + +/* Access Routines valid after a PCI-Access-Driver has registered */ +extern struct pci_access_drv pci_access_ops; + +/* Register PCI Access Driver */ +extern int pci_access_drv_register(struct pci_access_drv *drv); + +/* Set/unset bits in command and status register of a PCI device */ +extern void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val); + +/* Enable Memory in command register */ +static inline void pci_mem_enable(pci_dev_t dev) +{ + pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, PCI_COMMAND_MEMORY); +} + +static inline void pci_mem_disable(pci_dev_t dev) +{ + pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, 0); +} + +static inline void pci_io_enable(pci_dev_t dev) +{ + pci_modify_cmdsts(dev, PCI_COMMAND_IO, PCI_COMMAND_IO); +} + +static inline void pci_io_disable(pci_dev_t dev) +{ + pci_modify_cmdsts(dev, PCI_COMMAND_IO, 0); +} + +static inline void pci_master_enable(pci_dev_t dev) +{ + pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, PCI_COMMAND_MASTER); +} + +static inline void pci_master_disable(pci_dev_t dev) +{ + pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, 0); +} + +/* Configuration Space Access Read Routines */ +extern int pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *data); +extern int pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *data); +extern int pci_cfg_r32(pci_dev_t dev, int ofs, uint32_t *data); + +/* Configuration Space Access Write Routines */ +extern int pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t data); +extern int pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t data); +extern int pci_cfg_w32(pci_dev_t dev, int ofs, uint32_t data); + +/* Read a register over PCI I/O Space */ +extern uint8_t pci_io_r8(uint32_t adr); +extern uint16_t pci_io_r16(uint32_t adr); +extern uint32_t pci_io_r32(uint32_t adr); + +/* Write a register over PCI I/O Space */ +extern void pci_io_w8(uint32_t adr, uint8_t data); +extern void pci_io_w16(uint32_t adr, uint16_t data); +extern void pci_io_w32(uint32_t adr, uint32_t data); + +/* Translate PCI address into CPU accessible address */ +static inline int pci_pci2cpu(uint32_t *address, int type) +{ + return pci_access_ops.translate(address, type, 0); +} + +/* Translate CPU accessible address into PCI address (for DMA) */ +static inline int pci_cpu2pci(uint32_t *address, int type) +{ + return pci_access_ops.translate(address, type, 1); +} + +/*** Read/Write a register over PCI Memory Space ***/ + +static inline uint8_t pci_ld8(volatile uint8_t *addr) +{ + return *addr; +} + +static inline void pci_st8(volatile uint8_t *addr, uint8_t val) +{ + *addr = val; +} + +#ifdef BSP_PCI_BIG_ENDIAN + +/* BSP has decided Big Endian PCI Bus (non-standard) */ + +static inline uint16_t pci_ld_le16(volatile uint16_t *addr) +{ + return ld_be16(addr); +} + +static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val) +{ + st_be16(addr, val); +} + +static inline uint32_t pci_ld_le32(volatile uint32_t *addr) +{ + return ld_be32(addr); +} + +static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val) +{ + st_be32(addr, val); +} + +static inline uint16_t pci_ld_be16(volatile uint16_t *addr) +{ + return ld_le16(addr); +} + +static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val) +{ + st_le16(addr, val); +} + +static inline uint32_t pci_ld_be32(volatile uint32_t *addr) +{ + return ld_le32(addr); +} + +static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val) +{ + st_le32(addr, val); +} + +#else + +/* Little Endian PCI Bus */ + +static inline uint16_t pci_ld_le16(volatile uint16_t *addr) +{ + return ld_le16(addr); +} + +static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val) +{ + st_le16(addr, val); +} + +static inline uint32_t pci_ld_le32(volatile uint32_t *addr) +{ + return ld_le32(addr); +} + +static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val) +{ + st_le32(addr, val); +} + +static inline uint16_t pci_ld_be16(volatile uint16_t *addr) +{ + return ld_be16(addr); +} + +static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val) +{ + st_be16(addr, val); +} + +static inline uint32_t pci_ld_be32(volatile uint32_t *addr) +{ + return ld_be32(addr); +} + +static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val) +{ + st_be32(addr, val); +} + +#endif + +/* Get Read/Write function for accessing a register over PCI Memory Space + * (non-inline functions). + * + * Arguments + * wr 0(Read), 1(Write) + * size 1(Byte), 2(Word), 4(Double Word) + * func Where function pointer will be stored + * endian PCI_LITTLE_ENDIAN or PCI_BIG_ENDIAN + * type 1(I/O), 3(REG over MEM), 4(CFG) + * + * Return + * 0 Found function + * others No such function defined by host driver or BSP + */ +extern int pci_access_func(int wr, int size, void **func, int endian, int type); + +/* Predefined functions for Host drivers or BSPs that define the + * register-over-memory space functions operations. + */ +extern struct pci_memreg_ops pci_mem_le_ops; /* For Little-Endian PCI bus */ +extern struct pci_memreg_ops pci_mem_be_ops; /* For Big-Endian PCI bus */ + +#ifdef __cplusplus +} +#endif + +#endif /* !__PCI_ACCESS_H__ */ diff --git a/cpukit/libpci/pci/cfg.h b/cpukit/libpci/pci/cfg.h new file mode 100644 index 0000000000..6018ca5fa3 --- /dev/null +++ b/cpukit/libpci/pci/cfg.h @@ -0,0 +1,237 @@ +/* PCI Configuration Library, two versions of the library exists: + * - auto configuration (default) + * - static configuration (user defined config) + * both versions are defined here. + * + */ + +#ifndef __PCI_CFG_H__ +#define __PCI_CFG_H__ + +#include <pci.h> + +/* PCI Configuration library */ + +/* Return the number of PCI buses in system */ +extern int pci_bus_count(void); + +/* PCI Address assigned to BARs which failed to fit into the PCI Window or + * is disabled by any other cause. + */ +extern uint32_t pci_invalid_address; + +/* PCI Configuration Library of the system */ +enum { + PCI_CONFIG_LIB_NONE = 0, + PCI_CONFIG_LIB_AUTO = 1, + PCI_CONFIG_LIB_STATIC = 2, + PCI_CONFIG_LIB_READ = 3, + PCI_CONFIG_LIB_PERIPHERAL = 4, +}; +extern const int pci_config_lib_type; + +/* Configuration library function pointers, these are set in <rtems/confdefs.h> + * by project configuration or by the BSP. The configuration will pull in the + * PCI Library needed and the PCI initialization functions will call these + * functions on initialization from the host driver. + */ +extern int (*pci_config_lib_init)(void); +extern void (*pci_config_lib_register)(void *config); + +/* Configure PCI devices and bridges, and setup the RAM data structures + * describing the PCI devices currently present in the system. + * + * Returns 0 on success, -1 on failure. + */ +extern int pci_config_init(void); + +/* Register a config-library specific configuration used by the libarary in + * pci_config_init(). + */ +extern void pci_config_register(void *config); + +/* Print current PCI configuration (C-code) to terminal, can be used in + * static and peripheral PCI configuration library. The configuration is + * taken from the current configuration library setup. + */ +extern void pci_cfg_print(void); + +struct pci_bus; /* Bridge Device and secondary bus information */ +struct pci_dev; /* Device/function */ +struct pci_res; /* Resource: BAR, ROM or Bridge Window */ + +/* The Host Bridge and all subdevices (the PCI RAM data structure) */ +extern struct pci_bus pci_hb; + +/* Iterate over all PCI devices on a bus (see search options) and call func(), + * iteration is stopped if a non-zero value is returned by func(). + * + * The function iterates over the PCI RAM data structure, it is not + * available until after all devices have been found and pci_hb is populated, + * typically after pci_config_init() is called. + * + * search options: 0 (no child buses), 1 (depth first, recursive) + * + * Return Values + * 0 All PCI devices were processed, func() returned 0 on every call + * X func() returned non-zero X value, the search was stopped + */ +#define SEARCH_DEPTH 1 +extern int pci_for_each_child( + struct pci_bus *bus, + int (*func)(struct pci_dev *, void *arg), + void *arg, + int search); + +/* Depth first search of all PCI devices in PCI RAM data structure and call + * func(dev, arg), iteration is stopped if a non-zero value is returned by + * func(). + * + * The function iterates over the PCI RAM data structure, it is not + * available until after all devices have been found and pci_hb is populated, + * typically after pci_config_init() is called. + * + * Return Values + * 0 All PCI devices were processed, func() returned 0 on every call + * X func() returned non-zero X value, the search was stopped + */ +extern int pci_for_each_dev( + int (*func)(struct pci_dev *, void *arg), + void *arg); + +/* Get PCI device from RAM device tree for a device matching PCI Vendor, Device + * and instance number 'index'. + * + * Return Values + * -1 pci_find_dev did not find a device matching the criterion. + * 0 device was found, *ppdev was updated with the PCI device address + */ +extern int pci_find_dev(uint16_t ven, uint16_t dev, int index, + struct pci_dev **ppdev); + +/* Get PCI device from RAM device tree by BUS|SLOT|FUNC. + * + * Return Values + * -1 pci_get_dev did not find a device matching the criterion + * 0 device was found, *ppdev was updated with the PCI device address + */ +extern int pci_get_dev(pci_dev_t pcidev, struct pci_dev **ppdev); + +/* Resource flags */ +#define PCI_RES_IO 1 +#define PCI_RES_MEMIO 2 +#define PCI_RES_MEM_PREFETCH 1 +#define PCI_RES_MEM (PCI_RES_MEMIO | PCI_RES_MEM_PREFETCH) +#define PCI_RES_TYPE_MASK 0x3 +#define PCI_RES_IO32 0x08 +#define PCI_RES_FAIL 0x10 /* Alloc Failed */ + +/* BAR Resouces entry */ +struct pci_res { + struct pci_res *next; + uint32_t size; + uint32_t boundary; + unsigned char flags; /* I/O, MEM or MEMIO */ + unsigned char bar; + + /* Assigned Resource (PCI address), zero if not assigned */ + uint32_t start; + uint32_t end; +}; + +/* Get Device from resource pointer */ +#define RES2DEV(res) ((struct pci_dev *) \ + ((void *)res - (res->bar * (sizeof(struct pci_res))))) + +/* Device flags */ +#define PCI_DEV_BRIDGE 0x01 /* Device is a Bridge (struct pci_bus) */ +#define PCI_DEV_RES_FAIL 0x02 /* Resource alloction for device BARs failed */ + +/* Bus Flags */ +#define PCI_BUS_IO 0x01 /* 16-bit I/O address decoding */ +#define PCI_BUS_MEMIO 0x02 /* Bus support non-prefetchable mem (always) */ +#define PCI_BUS_MEM 0x04 /* Bus support prefetchable memory space */ +#define PCI_BUS_IO32 0x08 /* 32-bit I/O address decoding */ + +#define BRIDGE_RES_COUNT 2 /* Number of BAR resources a bridge can have */ +#define BUS_RES_START BRIDGE_RES_COUNT + +/* Bus Resources Array */ +enum { + BUS_RES_IO = 0, + BUS_RES_MEMIO = 1, + BUS_RES_MEM = 2, +}; + +/* Device Resource array index meaning */ +enum { + /* A Device has up to 6 BARs and an optional ROM BAR */ + DEV_RES_BAR1 = 0, + DEV_RES_BAR2 = 1, + DEV_RES_BAR3 = 2, + DEV_RES_BAR4 = 3, + DEV_RES_BAR5 = 4, + DEV_RES_BAR6 = 5, + DEV_RES_ROM = 6, + + /* Bridges have 2 BARs (BAR1 and BAR2) and 3 Windows to secondary bus + * and an optional ROM BAR + */ + BRIDGE_RES_BAR1 = 0, + BRIDGE_RES_BAR2 = 1, + BRIDGE_RES_IO = 2, + BRIDGE_RES_MEMIO = 3, + BRIDGE_RES_MEM = 4, + BRIDGE_RES_UNUSED1 = 5, + BRIDGE_RES_ROM = 6, +}; + +/* Maximum Number of Resources of a device */ +#define DEV_RES_CNT (DEV_RES_ROM + 1) + +/* PCI Device (Bus|Slot|Function) description */ +struct pci_dev { + struct pci_res resources[DEV_RES_CNT]; /* must be topmost field */ + struct pci_dev *next; + struct pci_bus *bus; + pci_dev_t busdevfun; + uint8_t flags; + uint8_t sysirq; + uint16_t vendor; + uint16_t device; + uint16_t subvendor; + uint16_t subdevice; + uint32_t classrev; + + /* static configuration settings */ + uint16_t command; +}; + +/* PCI Bus description */ +struct pci_bus { + struct pci_dev dev; /* PCI Bridge */ + struct pci_dev *devs; /* Devices on child (secondary) Bus */ + unsigned int flags; + + /* Bridge Information */ + int num; /* Bus number (0=Root-PCI-bus) */ + int pri; /* Primary Bus Number */ + int sord; /* Subordinate Buses (Child bus count) */ + +#if defined(PCI_CFG_AUTO_LIB) + /* Resources of devices on bus. USED INTERNALLY IN AUTO-CFG LIBRARY. + * + * BUS_RES_IO = 0: I/O resources + * BUS_RES_MEMIO = 1: Prefetchable memory resources + * BUS_RES_MEM = 2: Non-Prefetchable memory resources + */ + struct pci_res *busres[3]; +#endif +}; + +#include <pci/cfg_auto.h> +#include <pci/cfg_static.h> +#include <pci/cfg_read.h> +#include <pci/cfg_peripheral.h> + +#endif diff --git a/cpukit/libpci/pci/cfg_auto.h b/cpukit/libpci/pci/cfg_auto.h new file mode 100644 index 0000000000..aa55f501f6 --- /dev/null +++ b/cpukit/libpci/pci/cfg_auto.h @@ -0,0 +1,51 @@ +/* PCI Auto Configuration Library */ + +#ifndef __PCI_CFG_AUTO_H__ +#define __PCI_CFG_AUTO_H__ + +#define CFGOPT_NOSETUP_IRQ 0x1 /* Skip IRQ setup */ + +/* PCI Memory Layout setup, used by the auto-config library in order to + * determine the addresses of PCI BARs and Buses. + * + * All addresses are in PCI address space, the actual address the CPU access + * may be different, and taken care of elsewhere. + */ +struct pci_auto_setup { + int options; + + /* PCI prefetchable Memory space (OPTIONAL) */ + uint32_t mem_start; + uint32_t mem_size; /* 0 = Use MEMIO space for prefetchable mem BARs */ + + /* PCI non-prefetchable Memory */ + uint32_t memio_start; + uint32_t memio_size; + + /* PCI I/O space (OPTIONAL) */ + uint32_t io_start; + uint32_t io_size; /* 0 = No I/O space */ + + /* Get System IRQ connected to a PCI line of a PCI device on bus0. + * The return IRQ value zero equals no IRQ (IRQ disabled). + */ + uint8_t (*irq_map)(pci_dev_t dev, int irq_pin); + + /* IRQ Bridge routing. Returns the interrupt pin (0..3 = A..D) that + * a device is connected to on parent bus. + */ + int (*irq_route)(pci_dev_t dev, int irq_pin); +}; + +/* Do PCI initialization: Enumrate buses, scan buses for devices, assign + * I/O MEM and MEMIO resources, assign IRQ and so on. + */ +extern int pci_config_auto(void); + +/* Register a configuration for the auto library (struct pci_auto_setup *) */ +extern void pci_config_auto_register(void *config); + +/* PCI memory map */ +extern struct pci_auto_setup pci_auto_cfg; + +#endif diff --git a/cpukit/libpci/pci/cfg_peripheral.h b/cpukit/libpci/pci/cfg_peripheral.h new file mode 100644 index 0000000000..f54121d40c --- /dev/null +++ b/cpukit/libpci/pci/cfg_peripheral.h @@ -0,0 +1,12 @@ +/* PCI Peripheral Configuration Library */ + +#ifndef __PCI_CFG_PERIPHERAL_H__ +#define __PCI_CFG_PERIPHERAL_H__ + +/* The user must provide a PCI configuration using the "struct pci_bus pci_hb" + * structure. Nothing else than setting pci_system_type and pci_bus_cnt is done + * by the peripheral library. + */ +extern int pci_config_peripheral(void); + +#endif diff --git a/cpukit/libpci/pci/cfg_read.h b/cpukit/libpci/pci/cfg_read.h new file mode 100644 index 0000000000..09fe354736 --- /dev/null +++ b/cpukit/libpci/pci/cfg_read.h @@ -0,0 +1,14 @@ +/* PCI Read Configuration Library. Read current config that bootloader/BIOS + * has setup. + */ + +#ifndef __PCI_CFG_READ_H__ +#define __PCI_CFG_READ_H__ + +/* Build PCI device tree in "struct pci_bus pci_hb" according to current setup + * in hardware. Devices/buses are created by reading the resource assignments + * that the BIOS/bootloader has already setup for us. + */ +extern int pci_config_read(void); + +#endif diff --git a/cpukit/libpci/pci/cfg_static.h b/cpukit/libpci/pci/cfg_static.h new file mode 100644 index 0000000000..7d305c32aa --- /dev/null +++ b/cpukit/libpci/pci/cfg_static.h @@ -0,0 +1,14 @@ +/* Static PCI Auto Configuration Library */ + +#ifndef __PCI_CFG_STATIC_H__ +#define __PCI_CFG_STATIC_H__ + +/* This function initializes all buses and device accorind to a user defined + * "static" configuration. The configuration can manually created with C + * data structures. Or it can be automatically created on a running target + * using the pci_cfg_print() routine after the AUTO or READ Configuration + * Library has setup the PCI bus + */ +extern int pci_config_static(void); + +#endif diff --git a/cpukit/libpci/pci/ids.h b/cpukit/libpci/pci/ids.h new file mode 100644 index 0000000000..2d2592bc03 --- /dev/null +++ b/cpukit/libpci/pci/ids.h @@ -0,0 +1,802 @@ +/* PCI Identifiers - auto generated */ +#ifndef __PCI_IDS_H__ +#define __PCI_IDS_H__ + +/* Include non-public PCI ids (not auto generated) */ +#include <pci/ids_extra.h> + +/* Not a valid ID, used to match any device ID */ +#define PCI_ID_ANY 0xffff + +/* + * Vendor and card ID's: sort these numerically according to vendor + * (and according to card ID within vendor). Send all updates to + * <linux-pcisupport@cck.uni-kl.de>. + */ +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C875J 0x008f + +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215LG 0x4c47 +#define PCI_DEVICE_ID_ATI_264LT 0x4c54 +#define PCI_DEVICE_ID_ATI_264VT 0x5654 + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_82G2675 0x001d +#define PCI_DEVICE_ID_IBM_MCA 0x0020 +#define PCI_DEVICE_ID_IBM_82351 0x0022 +#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_MPIC 0x0046 +#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d +#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_7197 0x3296 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_601 0x0601 +#define PCI_DEVICE_ID_SI_5107 0x5107 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_7001 0x7001 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_92C178 0xc178 +#define PCI_DEVICE_ID_OPTI_82C557 0xc557 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C701 0xc701 +#define PCI_DEVICE_ID_OPTI_82C814 0xc814 +#define PCI_DEVICE_ID_OPTI_82C822 0xc822 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_SGS 0x104a +#define PCI_DEVICE_ID_SGS_2000 0x0008 +#define PCI_DEVICE_ID_SGS_1764 0x0009 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_PCI1130 0xac12 +#define PCI_DEVICE_ID_TI_PCI1031 0xac13 +#define PCI_DEVICE_ID_TI_PCI1131 0xac15 +#define PCI_DEVICE_ID_TI_PCI1250 0xac16 +#define PCI_DEVICE_ID_TI_PCI1220 0xac17 + +#define PCI_VENDOR_ID_OAK 0x104e +#define PCI_DEVICE_ID_OAK_OTI107 0x0107 + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_5300 0x5300 + +#define PCI_VENDOR_ID_N9 0x105d +#define PCI_DEVICE_ID_N9_I128 0x2309 +#define PCI_DEVICE_ID_N9_I128_2 0x2339 +#define PCI_DEVICE_ID_N9_I128_T2R 0x493d + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 +#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 +#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 +#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 +#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 + +#define PCI_VENDOR_ID_X 0x1061 +#define PCI_DEVICE_ID_X_AGX016 0x0001 + +#define PCI_VENDOR_ID_PICOP 0x1066 +#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 +#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_GC 0x0002 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e + +#define PCI_VENDOR_ID_NEXGEN 0x1074 +#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_LEADTEK 0x107d +#define PCI_DEVICE_ID_LEADTEK_805 0x0000 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_FOREX 0x1083 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 +#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_CMD_640 0x0640 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_647 0x0647 +#define PCI_DEVICE_ID_CMD_670 0x0670 + +#define PCI_VENDOR_ID_VISION 0x1098 +#define PCI_DEVICE_ID_VISION_QD8500 0x0001 +#define PCI_DEVICE_ID_VISION_QD8580 0x0002 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 +#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 +#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 + +#define PCI_VENDOR_ID_SIERRA 0x10a8 +#define PCI_DEVICE_ID_SIERRA_STB 0x0000 + +#define PCI_VENDOR_ID_ACC 0x10aa +#define PCI_DEVICE_ID_ACC_2056 0x0000 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_83769 0x0001 +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_DATABOOK 0x10b3 +#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9060 0x9060 +#define PCI_DEVICE_ID_PLX_9060ES 0x906E +#define PCI_DEVICE_ID_PLX_9060SD 0x906D +#define PCI_DEVICE_ID_PLX_9080 0x9080 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 +#define PCI_DEVICE_ID_MADGE_C155S 0x1001 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C590 0x5900 +#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 +#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 +#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 +#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 +#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 +#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 +#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 +#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 + +#define PCI_VENDOR_ID_SMC 0x10b8 +#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1445 0x1445 +#define PCI_DEVICE_ID_AL_M1449 0x1449 +#define PCI_DEVICE_ID_AL_M1451 0x1451 +#define PCI_DEVICE_ID_AL_M1461 0x1461 +#define PCI_DEVICE_ID_AL_M1489 0x1489 +#define PCI_DEVICE_ID_AL_M1511 0x1511 +#define PCI_DEVICE_ID_AL_M1513 0x1513 +#define PCI_DEVICE_ID_AL_M1521 0x1521 +#define PCI_DEVICE_ID_AL_M1523 0x1523 +#define PCI_DEVICE_ID_AL_M1531 0x1531 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M3307 0x3307 +#define PCI_DEVICE_ID_AL_M4803 0x5215 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5237 0x5237 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_MITSUBISHI 0x10ba + +#define PCI_VENDOR_ID_SURECOM 0x10bd +#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 + +#define PCI_VENDOR_ID_ASP 0x10cd +#define PCI_DEVICE_ID_ASP_ABP940 0x1200 +#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 +#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 + +#define PCI_VENDOR_ID_MACRONIX 0x10d9 +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 + +#define PCI_VENDOR_ID_CERN 0x10dc +#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 +#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 +#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 +#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 + +#define PCI_VENDOR_ID_NVIDIA 0x10de + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_8849 0x8849 + +#define PCI_VENDOR_ID_TEKRAM2 0x10e1 +#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c + +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 +#define PCI_DEVICE_ID_AMCC_S5933 0x807d +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1680 0x1680 +#define PCI_DEVICE_ID_INTERG_1682 0x1682 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8129 0x8129 +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 + +#define PCI_VENDOR_ID_TRUEVISION 0x10fa +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c + +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_DEVICE_ID_INIT_320P 0x9100 +#define PCI_DEVICE_ID_INIT_360P 0x9500 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_82C505 0x0505 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C585 0x0585 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C595 0x0595 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C926 0x0926 +#define PCI_DEVICE_ID_VIA_82C416 0x1571 +#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_86C100A 0x6100 +#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_IMAGINGTECH 0x112f +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 + +#define PCI_VENDOR_ID_CYCLONE 0x113c +#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 + +#define PCI_VENDOR_ID_ALLIANCE 0x1142 +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 +#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 +#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d + +#define PCI_VENDOR_ID_SK 0x1148 +#define PCI_DEVICE_ID_SK_FP 0x4000 +#define PCI_DEVICE_ID_SK_TR 0x4200 +#define PCI_DEVICE_ID_SK_GE 0x4300 + +#define PCI_VENDOR_ID_VMIC 0x114a +#define PCI_DEVICE_ID_VMIC_VME 0x7587 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_EPC 0x0002 +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 +#define PCI_DEVICE_ID_DIGI_XEM 0x0004 +#define PCI_DEVICE_ID_DIGI_XR 0x0005 +#define PCI_DEVICE_ID_DIGI_CX 0x0006 +#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 +#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a +#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 + +#define PCI_VENDOR_ID_MUTECH 0x1159 +#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 + +#define PCI_VENDOR_ID_RENDITION 0x1163 +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_OMEGA 0x119b +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 + +#define PCI_VENDOR_ID_LITEON 0x11ad +#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 + +#define PCI_VENDOR_ID_NP 0x11bc +#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 +#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 +#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 + +#define PCI_VENDOR_ID_AURAVISION 0x11d1 +#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 + +#define PCI_VENDOR_ID_IKON 0x11d5 +#define PCI_DEVICE_ID_IKON_10115 0x0115 +#define PCI_DEVICE_ID_IKON_10117 0x0117 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_KINETIC 0x11f4 +#define PCI_DEVICE_ID_KINETIC_2915 0x2915 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 +#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP8M 0x000C + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 + +#define PCI_VENDOR_ID_SIGMADES 0x1236 +#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 + +#define PCI_VENDOR_ID_CCUBE 0x123f + +#define PCI_VENDOR_ID_DIPIX 0x1246 + +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 +#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 + +#define PCI_VENDOR_ID_OPTIBASE 0x1255 +#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 +#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 +#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 +#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b + +#define PCI_VENDOR_ID_HUGHES 0x1273 +#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI 0x5000 + +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 + +#define PCI_VENDOR_ID_PICTUREL 0x12c5 +#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_VENDOR_ID_CBOARDS 0x1307 +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 + +#define PCI_VENDOR_ID_SYMPHONY 0x1c1c +#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 +#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 +#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 + +#define PCI_VENDOR_ID_AVANCE 0x4005 +#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 +#define PCI_DEVICE_ID_AVANCE_2302 0x2302 + +#define PCI_VENDOR_ID_NETVIN 0x4a14 +#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +#define PCI_DEVICE_ID_S3_ViRGE 0x5631 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 +#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 +#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_928 0x88b0 +#define PCI_DEVICE_ID_S3_864_1 0x88c0 +#define PCI_DEVICE_ID_S3_864_2 0x88c1 +#define PCI_DEVICE_ID_S3_964_1 0x88d0 +#define PCI_DEVICE_ID_S3_964_2 0x88d1 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 +#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 +#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 +#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 +#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 +#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_82430 0x0486 +#define PCI_DEVICE_ID_INTEL_82434 0x04a3 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_82596 0x1226 +#define PCI_DEVICE_ID_INTEL_82865 0x1227 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_P6 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 + +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f + +#define PCI_VENDOR_ID_ATRONICS 0x907f +#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 + +#define PCI_VENDOR_ID_ARK 0xedd8 +#define PCI_DEVICE_ID_ARK_STING 0xa091 +#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 +#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + +#endif /* !__PCI_IDS_H__ */ diff --git a/cpukit/libpci/pci/ids_extra.h b/cpukit/libpci/pci/ids_extra.h new file mode 100644 index 0000000000..ffa18cb271 --- /dev/null +++ b/cpukit/libpci/pci/ids_extra.h @@ -0,0 +1,19 @@ +/* RTEMS local PCI data base */ + +/* Only included from pci_ids.h */ +#ifndef __PCI_IDS_H__ +#error pci/ids_extra.h should only be included from pci/ids.h +#endif + +/* Gaisler PCI IDs */ +#define PCIID_VENDOR_GAISLER 0x1AC8 +#define PCIID_VENDOR_GAISLER_OLD 0x16E3 + +/* Gaisler PCI Devices */ +#define PCIID_DEVICE_GR_RASTA_IO 0x0010 /* GR-RASTA-IO */ +#define PCIID_DEVICE_GR_RASTA_IO_OLD 0x0210 /* old GR-RASTA-IO ID*/ +#define PCIID_DEVICE_GR_RASTA_TMTC 0x0011 /* GR-RASTA-TMTC */ +#define PCIID_DEVICE_GR_RASTA_ADCDAC 0x0014 /* GR-RASTA-ADCDAC */ +#define PCIID_DEVICE_GR_701 0x0701 /* GR-701 */ +#define PCIID_DEVICE_GR_TMTC_1553 0x0198 /* GR-TMTC-1553 */ +#define PCIID_DEVICE_GR_RASTA_SPW_RTR 0x0062 /* GR-RASTA-SPW-ROUTER */ diff --git a/cpukit/libpci/pci/irq.h b/cpukit/libpci/pci/irq.h new file mode 100644 index 0000000000..87ca154073 --- /dev/null +++ b/cpukit/libpci/pci/irq.h @@ -0,0 +1,98 @@ +/* PCI IRQ Library + * + * IRQ handling does not have so much with PCI to do, this library depends + * on the BSP to implement shared interrupts. + */ + +#ifndef __PCI_IRQ_H__ +#define __PCI_IRQ_H__ + +#include <bsp.h> + +/* PCI Handler (ISR) called when IRQ is generated by any of the PCI devices + * connected to the same PCI IRQ Pin. This is been defined the same way as + * rtems_interrupt_handler in order for BSPs to "direct-map" the register + * and unregister functions rtems_interrupt_handler_install/remove + */ +typedef void (*pci_isr)(void *arg); + +/* Get assigned system IRQ to a PCI Device. If no IRQ 0 is returned */ +extern int pci_dev_irq(pci_dev_t dev); + +/* Register shared PCI IRQ handler, but does not enable it. The system interrupt + * number is read from the PCI board's PCI configuration space header iline + * field. The iline field is initialized by the PCI subsystem during start up, + * the ipin field is translated into a system IRQ and written to iline. The + * board's driver should use the iline field as the irq argument to this + * function. + * + * Arguments + * irq System IRQ number, normally taken from the PCI configuration area + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static inline int pci_interrupt_register(int irq, const char *info, + pci_isr isr, void *arg) +{ + return BSP_PCI_shared_interrupt_register(irq, info, isr, arg); +} + +/* Unregister previously registered shared PCI IRQ handler + * + * Arguments + * irq System IRQ number, normally taken from the PCI configuration area + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static inline int pci_interrupt_unregister(int irq, pci_isr isr, void *arg) +{ + return BSP_PCI_shared_interrupt_unregister(irq, isr, arg); +} + +/* Enable shared PCI IRQ handler. This function will unmask the interrupt + * controller and mark this interrupt handler ready to handle interrupts. Note + * that since it is a shared interrupt handler service the interrupt may + * already be enabled, however no calls to this specific handler is made + * until it is enabled. + * + * Arguments + * irq System IRQ number, normally taken from the PCI configuration area + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static inline void pci_interrupt_unmask(int irq) +{ + BSP_PCI_shared_interrupt_unmask(irq); +} + +/* Disable shared PCI IRQ handler. This function will mask the interrupt + * controller and mark this interrupt handler not ready to receive interrupts. + * Note that since it is a shared interrupt handler service the interrupt may + * still be enabled, however no calls to this specific handler is made + * while it is disabled. + * + * Arguments + * irq System IRQ number, normally taken from the PCI configuration area + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static inline void pci_interrupt_mask(int irq) +{ + BSP_PCI_shared_interrupt_mask(irq); +} + +/* Acknowledge the interrupt controller by writing to the interrupt controller. + * Note that since it is a shared interrupt handler service, clearing the + * interrupt source may affect other ISRs registered to this IRQ. + * + * Arguments + * irq System IRQ number, normally taken from the PCI configuration area + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static inline void pci_interrupt_clear(int irq) +{ + BSP_PCI_shared_interrupt_clear(irq); +} + +#endif /* !__PCI_IRQ_H__ */ |