leon,tn-0018: work around GRLIB-TN-0018 erratarcc-v1.2.24rcc-1.2

The errata is worked around in the kernel without requiring toolchain
modifications. It is triggered the JMPL/RETT return from trap instruction
sequence never generated by the compiler and. There are also other
conditions that must must be true to trigger the errata, for example the
instruction that the trap returns to has to be a JMPL instruction. The
errata can only be triggered if certain data is corrected by ECC
(inflicted by radiation), thus it can not be triggered under normal
operation. For more information see:
       www.gaisler.com/notes

Affected RTEMS target BSPs:
  * GR712RC
  * UT699
  * UT700/699E

The work around is enabled by defining __FIX_LEON3_TN0018 at build time
for the leon3 BSP.

In general there are two approaches that the workaround uses:
  A) avoid ECC restarting the RETT instruction
  B) avoid returning from trap to a JMPL instruction

Where A) comes at a higher performance cost than B), so B) is used
where posssible. B) can be achived for certain returns from trap
handlers if trap entry is controlled by assembly, such as system calls.

A)
A special JMPL/RETT sequence where instruction cache is disabled
temporarily to avoid RETT containing ECC errors, and reading of RETT
source registers to "clean" them from incorrect ECC just before RETT
is executed.

B)
The work around prevents JMPL after system calls (TA instruction) and
modifies assembly code on return from traps jumping back to application
code. Note that for some traps the trapped instruction is always
re-executed and can therefore not trigger the errata, for example the
SAVE instruction causing window overflow or an float instruction causing
FPU disabled trap.

RTEMS SPARC traps workaround implementation:
   NAME                  NOTE   TRAP   COMMENT
 * window overflow          1 - 0x05   always returns to a SAVE
 * window underflow         1 - 0x06   always returns to a RESTORE
 * interrupt traps          2 - 0x10..1f special rett sequence workaround
 * syscall                  3 - 0x80   shutdown system - never returns
 * ABI flush windows        2 - 0x83   special rett sequence workaround
 * sparc_disable_interrupts 4 - 0x80
 * sparc_enable_interrupts  4 - 0x8A
 * syscall_irqdis_fp        1 - 0x8B   always jumps back to FP instruction

 Notes:
 1) no workaround needed because trap always returns to non-JMPL instruction
 2) workaround implemented by special rett sequence
 3) no workaround needed because system call never returns
 4) workaround implemented by inserting NOP in system call generation. Thus
    fall into 1) when workaround is enabled and no trap handler fix needed.

Any custom trap handlers may also have to be updated. To simplify that,
helper work around assembly code in macros are available in a separate
include file <rtems/score/grlib-tn-0018.h>.

7 files changed, 79 insertions, 3 deletions

diff --git a/c/src/lib/libbsp/sparc/leon3/make/custom/leon3.cfg b/c/src/lib/libbsp/sparc/leon3/make/custom/leon3.cfg
index 48f125b551..14cd029513 100644
--- a/c/src/lib/libbsp/sparc/leon3/make/custom/leon3.cfg
+++ b/c/src/lib/libbsp/sparc/leon3/make/custom/leon3.cfg
@@ -11,7 +11,8 @@ RTEMS_CPU_MODEL=leon3
 
 #  This contains the compiler options necessary to select the CPU model
 #  and (hopefully) optimize for it.
-CPU_CFLAGS = -mcpu=cypress -msoft-float -mtune=ut699 -mfix-ut700 -mfix-gr712rc
+CPU_CFLAGS = -mcpu=cypress -msoft-float -mtune=ut699 -mfix-ut700 -mfix-gr712rc -D__FIX_LEON3FT_TN0018
+# -D__FIX_LEON3FT_TN0018 enables kernel work around for GRLIB-TN-0018 errata
 
 # optimize flag: typically -O2
 CFLAGS_OPTIMIZE_V = -O2 -g
diff --git a/c/src/lib/libcpu/sparc/reg_win/window.S b/c/src/lib/libcpu/sparc/reg_win/window.S
index fa327ec28a..3c3443f850 100644
--- a/c/src/lib/libcpu/sparc/reg_win/window.S
+++ b/c/src/lib/libcpu/sparc/reg_win/window.S
@@ -24,6 +24,8 @@
  */
 
 #include <rtems/asm.h>
+#include <rtems/score/grlib-tn-0018.h>
+
 
         .seg    "text"
         /*
@@ -254,12 +256,18 @@ done_flushing:
          *  Restore the global registers we used
          */
 
-        mov     %l3, %g1
         mov     %l4, %g2
         mov     %l5, %g3
+
+        TN0018_WAIT_IFLUSH %l4,%l5
+        TN0018_WRITE_PSR %g1
+
+        mov     %l3, %g1
         mov     %l6, %g4
         mov     %l7, %g5
 
+        TN0018_FIX %l4,%l5
+
         jmpl    %l2, %g0
         rett    %l2 + 4
 
diff --git a/c/src/lib/libcpu/sparc/syscall/syscall.S b/c/src/lib/libcpu/sparc/syscall/syscall.S
index aa69f45d48..029027e7c9 100644
--- a/c/src/lib/libcpu/sparc/syscall/syscall.S
+++ b/c/src/lib/libcpu/sparc/syscall/syscall.S
@@ -63,6 +63,7 @@ SYM(sparc_disable_interrupts):
 
 	mov	SYS_irqdis, %g1
 	ta	0
+	nop
 	retl
 	nop
 
@@ -72,6 +73,7 @@ SYM(sparc_enable_interrupts):
 
 	mov	SYS_irqen, %g1
 	ta	0
+	nop
 	retl
 	nop
 
diff --git a/cpukit/score/cpu/sparc/Makefile.am b/cpukit/score/cpu/sparc/Makefile.am
index 6d4c4aead1..714d2e1c1b 100644
--- a/cpukit/score/cpu/sparc/Makefile.am
+++ b/cpukit/score/cpu/sparc/Makefile.am
@@ -9,7 +9,7 @@ include_rtems_HEADERS = rtems/asm.h
 
 include_rtems_scoredir = $(includedir)/rtems/score
 include_rtems_score_HEADERS = rtems/score/sparc.h rtems/score/cpu.h \
-    rtems/score/types.h
+    rtems/score/types.h rtems/score/grlib-tn-0018.h
 
 noinst_LIBRARIES = libscorecpu.a
 libscorecpu_a_SOURCES = cpu.c cpu_asm.S
diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S
index 7cf698e51b..fa2262a8af 100644
--- a/cpukit/score/cpu/sparc/cpu_asm.S
+++ b/cpukit/score/cpu/sparc/cpu_asm.S
@@ -26,6 +26,7 @@
 #endif
 
 #include <rtems/asm.h>
+#include <rtems/score/grlib-tn-0018.h>
 
 #if (SPARC_HAS_FPU == 1)
 
@@ -937,11 +938,13 @@ simple_return:
         save                               ! Back to ISR dispatch window
 
 good_task_window:
+        TN0018_WAIT_IFLUSH %l3,%l4         ! GRLIB-TN-0018 work around macro
 
         mov     %l0, %psr                  !  **** DISABLE TRAPS ****
 	nop; nop; nop
                                            !  and restore condition codes.
         ld      [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
+        TN0018_FIX %l3,%l4                 ! GRLIB-TN-0018 work around macro
         jmp     %l1                        ! transfer control and
         rett    %l2                        ! go back to tasks window
 
diff --git a/cpukit/score/cpu/sparc/preinstall.am b/cpukit/score/cpu/sparc/preinstall.am
index da9dde121f..bf7045abdc 100644
--- a/cpukit/score/cpu/sparc/preinstall.am
+++ b/cpukit/score/cpu/sparc/preinstall.am
@@ -39,3 +39,7 @@ $(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/r
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
 
+$(PROJECT_INCLUDE)/rtems/score/grlib-tn-0018.h: rtems/score/grlib-tn-0018.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/grlib-tn-0018.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/grlib-tn-0018.h
+
diff --git a/cpukit/score/cpu/sparc/rtems/score/grlib-tn-0018.h b/cpukit/score/cpu/sparc/rtems/score/grlib-tn-0018.h
new file mode 100644
index 0000000000..f0154ab636
--- /dev/null
+++ b/cpukit/score/cpu/sparc/rtems/score/grlib-tn-0018.h
@@ -0,0 +1,58 @@
+/* NOTE: the lda should be on offset 0x18 */
+#if defined(__FIX_LEON3FT_TN0018)
+
+/* LEON3 Cache controller register accessed via ASI 2 */
+#define ASI_CTRL 0x02
+#define CCTRL_IP_BIT 15
+#define CCTRL_ICS 0x3
+
+/*
+ * l3: (out) original cctrl
+ * l4: (out) original cctrl with ics=0
+ * NOTE: This macro modifies psr.icc.
+ */
+.macro TN0018_WAIT_IFLUSH out1 out2
+1:
+        ! wait for pending iflush to complete
+        lda     [%g0] ASI_CTRL, \out1
+        srl     \out1, CCTRL_IP_BIT, \out2
+        andcc   \out2, 1, %g0
+        bne     1b
+         andn   \out1, CCTRL_ICS, \out2
+.endm
+
+
+.macro TN0018_WRITE_PSR src
+        wr      \src, %psr
+.endm
+
+/* Prevent following jmp;rett sequence from "re-executing" due to cached RETT or source
+ * registers (l1 and l2) containing bit faults triggering ECC.
+ *
+ * l3: (in) original cctrl
+ * l4: (in) original cctrl with ics=0
+ * NOTE: This macro MUST be immediately followed by the "jmp;rett" pair.
+ */
+.macro TN0018_FIX in1 in2
+        .align  0x20                    ! align the sta for performance
+        sta     \in2, [%g0] ASI_CTRL    ! disable icache
+        nop                             ! delay for sta to have effect on rett
+        or      %l1, %l1, %l1           ! delay + catch rf parity error on l1
+        or      %l2, %l2, %l2           ! delay + catch rf parity error on l2
+        sta     \in1, [%g0] ASI_CTRL     ! re-enable icache after rett
+        nop                             ! delay ensures insn after gets cached
+.endm
+
+#else
+
+.macro TN0018_WAIT_IFLUSH out1 out2
+.endm
+
+.macro TN0018_WRITE_PSR src
+.endm
+
+.macro TN0018_FIX in1 in2
+.endm
+
+#endif
+