diff options
Diffstat (limited to 'include/sparc')
48 files changed, 3598 insertions, 0 deletions
diff --git a/include/sparc/erc32/bsp.h b/include/sparc/erc32/bsp.h new file mode 100644 index 0000000000..33939106d8 --- /dev/null +++ b/include/sparc/erc32/bsp.h @@ -0,0 +1,191 @@ +/** + * @file + * + * @ingroup sparc_erc32 + * + * @brief Global BSP Definitions. + */ + +/* + * COPYRIGHT (c) 1989-2007. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to ERC32 implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef _BSP_H +#define _BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <rtems/iosupp.h> +#include <erc32.h> +#include <rtems/clockdrv.h> +#include <rtems/console.h> +#include <rtems/irq-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sparc_erc32 ERC32 Support + * + * @ingroup bsp_sparc + * + * @brief ERC32 Support Package + */ + +/* + * BSP provides its own Idle thread body + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_erc32_sonic_driver_attach( + struct rtems_bsdnet_ifconfig *config +); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; + +extern int end; /* last address in the program */ + +/* functions */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +void BSP_fatal_exit(uint32_t error); + +void bsp_spurious_initialize( void ); + +/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function + * can be called at any time. The work-area will shrink when called before + * bsp_work_area_initialize(). malloc() is called to get memory when this + * function is called after bsp_work_area_initialize(). + */ +void *bsp_early_malloc(int size); + +/* Interrupt Service Routine (ISR) pointer */ +typedef void (*bsp_shared_isr)(void *arg); + +/* Initializes the Shared System Interrupt service */ +extern void BSP_shared_interrupt_init(void); + +/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple + * interrupt handlers may use the same IRQ number, all ISRs will be called + * when an interrupt on that line is fired. + * + * Arguments + * irq System IRQ number + * info Optional Name of IRQ source + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_register + ( + int irq, + const char *info, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_install(irq, info, + RTEMS_INTERRUPT_SHARED, isr, arg); +} + +/* Unregister previously registered shared IRQ handler. + * + * Arguments + * irq System IRQ number + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_unregister + ( + int irq, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_remove(irq, isr, arg); +} + +/* Clear interrupt pending on IRQ controller, this is typically done on a + * level triggered interrupt source such as PCI to avoid taking double IRQs. + * In such a case the interrupt source must be cleared first on LEON, before + * acknowledging the IRQ with this function. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_clear(int irq); + +/* Enable Interrupt. This function will unmask the IRQ at the interrupt + * controller. This is normally done by _register(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_unmask(int irq); + +/* Disable Interrupt. This function will mask one IRQ at the interrupt + * controller. This is normally done by _unregister(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_mask(int irq); + +/* + * Delay for the specified number of microseconds. + */ +void rtems_bsp_delay(int usecs); + +/* + * Prototypes for methods used across file boundaries + */ +void console_outbyte_polled(int port, unsigned char ch); +int console_inbyte_nonblocking(int port); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/sparc/erc32/bsp/irq.h b/include/sparc/erc32/bsp/irq.h new file mode 100644 index 0000000000..e0bc3393d8 --- /dev/null +++ b/include/sparc/erc32/bsp/irq.h @@ -0,0 +1,28 @@ +/** + * @file + * @ingroup sparc_erc32 + * @brief ERC32 generic shared IRQ setup + * + * Based on libbsp/shared/include/irq.h. + */ + +/* + * Copyright (c) 2012. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ERC32_IRQ_CONFIG_H +#define LIBBSP_ERC32_IRQ_CONFIG_H + +#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD + +/* No extra check is needed */ +#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR + +#endif /* LIBBSP_ERC32_IRQ_CONFIG_H */ diff --git a/include/sparc/erc32/coverhd.h b/include/sparc/erc32/coverhd.h new file mode 100644 index 0000000000..51037e4129 --- /dev/null +++ b/include/sparc/erc32/coverhd.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/coverhd.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/coverhd.h> diff --git a/include/sparc/erc32/libcpu/byteorder.h b/include/sparc/erc32/libcpu/byteorder.h new file mode 100644 index 0000000000..10b4239480 --- /dev/null +++ b/include/sparc/erc32/libcpu/byteorder.h @@ -0,0 +1,66 @@ +/* + * byteorder.h - Endian conversion for SPARC. SPARC is big endian only. + * + * COPYRIGHT (c) 2011 + * Aeroflex Gaisler. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_BYTEORDER_H +#define _LIBCPU_BYTEORDER_H + +#include <rtems/system.h> +#include <rtems/score/cpu.h> + +#ifdef __cplusplus +extern "C" { +#endif + +RTEMS_INLINE_ROUTINE uint16_t ld_le16(volatile uint16_t *addr) +{ + return CPU_swap_u16(*addr); +} + +RTEMS_INLINE_ROUTINE void st_le16(volatile uint16_t *addr, uint16_t val) +{ + *addr = CPU_swap_u16(val); +} + +RTEMS_INLINE_ROUTINE uint32_t ld_le32(volatile uint32_t *addr) +{ + return CPU_swap_u32(*addr); +} + +RTEMS_INLINE_ROUTINE void st_le32(volatile uint32_t *addr, uint32_t val) +{ + *addr = CPU_swap_u32(val); +} + +RTEMS_INLINE_ROUTINE uint16_t ld_be16(volatile uint16_t *addr) +{ + return *addr; +} + +RTEMS_INLINE_ROUTINE void st_be16(volatile uint16_t *addr, uint16_t val) +{ + *addr = val; +} + +RTEMS_INLINE_ROUTINE uint32_t ld_be32(volatile uint32_t *addr) +{ + return *addr; +} + +RTEMS_INLINE_ROUTINE void st_be32(volatile uint32_t *addr, uint32_t val) +{ + *addr = val; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/sparc/erc32/rtems/asm.h b/include/sparc/erc32/rtems/asm.h new file mode 100644 index 0000000000..a2b11f63fc --- /dev/null +++ b/include/sparc/erc32/rtems/asm.h @@ -0,0 +1,120 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif + +#include <rtems/score/cpuopts.h> +#include <rtems/score/cpu.h> + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ +/* XXX The following ifdef magic fixes the problem but results in a warning */ +/* XXX when compiling assembly code. */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include <rtems/concat.h> + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +/* + * Entry for traps which jump to a programmer-specified trap handler. + */ + +#define TRAP(_vector, _handler) \ + mov %psr, %l0 ; \ + sethi %hi(_handler), %l4 ; \ + jmp %l4+%lo(_handler); \ + mov _vector, %l3 + +/* + * Used for the reset trap to avoid a supervisor instruction + */ + +#define RTRAP(_vector, _handler) \ + mov %g0, %l0 ; \ + sethi %hi(_handler), %l4 ; \ + jmp %l4+%lo(_handler); \ + mov _vector, %l3 + +#endif diff --git a/include/sparc/erc32/rtems/score/cpu.h b/include/sparc/erc32/rtems/score/cpu.h new file mode 100644 index 0000000000..6ce065cfe4 --- /dev/null +++ b/include/sparc/erc32/rtems/score/cpu.h @@ -0,0 +1,1368 @@ +/** + * @file + * + * @brief SPARC CPU Department Source + * + * This include file contains information pertaining to the port of + * the executive to the SPARC processor. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems/score/types.h> +#include <rtems/score/sparc.h> + +/* conditional compilation parameters */ + +/** + * Should the calls to _Thread_Enable_dispatch be inlined? + * + * - If TRUE, then they are inlined. + * - If FALSE, then a subroutine call is made. + * + * On this port, it is faster to inline _Thread_Enable_dispatch. + */ +#define CPU_INLINE_ENABLE_DISPATCH TRUE + +/** + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * - If TRUE, then the loops are unrolled. + * - If FALSE, then the loops are not unrolled. + * + * This parameter could go either way on the SPARC. The interrupt flash + * code is relatively lengthy given the requirements for nops following + * writes to the psr. But if the clock speed were high enough, this would + * not represent a great deal of time. + */ +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +/** + * Does the executive manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * The SPARC does not have a dedicated HW interrupt stack and one has + * been implemented in SW. + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/** + * Does the CPU follow the simple vectored interrupt model? + * + * - If TRUE, then RTEMS allocates the vector table it internally manages. + * - If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * THe SPARC is a simple vectored architecture. Usually there is no + * PIC and the CPU directly vectors the interrupts. + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * - If TRUE, then it must be installed during initialization. + * - If FALSE, then no installation is performed. + * + * The SPARC does not have a dedicated HW interrupt stack. + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/** + * Do we allocate a dedicated interrupt stack in the Interrupt Manager? + * + * - If TRUE, then the memory is allocated during initialization. + * - If FALSE, then the memory is allocated during initialization. + * + * The SPARC does not have hardware support for switching to a + * dedicated interrupt stack. The port includes support for doing this + * in software. + * + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + * The SPARC port does not pass an Interrupt Stack Frame pointer to + * interrupt handlers. + */ +#define CPU_ISR_PASSES_FRAME_POINTER 0 + +/** + * Does the CPU have hardware floating point? + * + * - If TRUE, then the FLOATING_POINT task attribute is supported. + * - If FALSE, then the FLOATING_POINT task attribute is ignored. + * + * This is set based upon the multilib settings. + */ +#if ( SPARC_HAS_FPU == 1 ) + #define CPU_HARDWARE_FP TRUE +#else + #define CPU_HARDWARE_FP FALSE +#endif + +/** + * The SPARC GCC port does not have a software floating point library + * that requires RTEMS assistance. + */ +#define CPU_SOFTWARE_FP FALSE + +/** + * Are all tasks FLOATING_POINT tasks implicitly? + * + * - If TRUE, then the FLOATING_POINT task attribute is assumed. + * - If FALSE, then the FLOATING_POINT task attribute is followed. + * + * The SPARC GCC port does not implicitly use floating point registers. + */ +#define CPU_ALL_TASKS_ARE_FP FALSE + +/** + * Should the IDLE task have a floating point context? + * + * - If TRUE, then the IDLE task is created as a FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * - If FALSE, then the IDLE task does not have a floating point context. + * + * The IDLE task does not have to be floating point on the SPARC. + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/** + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * - If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * - If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * On the SPARC, we can disable the FPU for integer only tasks so + * it is safe to defer floating point context switches. + */ +#if defined(RTEMS_SMP) + #define CPU_USE_DEFERRED_FP_SWITCH FALSE +#else + #define CPU_USE_DEFERRED_FP_SWITCH TRUE +#endif + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * - If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * - If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * The SPARC architecture does not have a low power or halt instruction. + * It is left to the BSP and/or CPU specific code to provide an IDLE + * thread body which is aware of low power modes. + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * - If TRUE, then the grows upward. + * - If FALSE, then the grows toward smaller addresses. + * + * The stack grows to lower addresses on the SPARC. + */ +#define CPU_STACK_GROWS_UP FALSE + +/** + * The following is the variable attribute used to force alignment + * of critical data structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The SPARC does not appear to have particularly strict alignment + * requirements. This value was chosen to take advantages of caches. + */ +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) + +#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE + +/** + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * The SPARC is big endian. + */ +#define CPU_BIG_ENDIAN TRUE + +/** + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * The SPARC is NOT little endian. + */ +#define CPU_LITTLE_ENDIAN FALSE + +/** + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + * The SPARC has 16 interrupt levels in the PIL field of the PSR. + */ +#define CPU_MODES_INTERRUPT_MASK 0x0000000F + +#ifndef ASM +/** + * This structure represents the organization of the minimum stack frame + * for the SPARC. More framing information is required in certain situaions + * such as when there are a large number of out parameters or when the callee + * must save floating point registers. + */ +typedef struct { + /** This is the offset of the l0 register. */ + uint32_t l0; + /** This is the offset of the l1 register. */ + uint32_t l1; + /** This is the offset of the l2 register. */ + uint32_t l2; + /** This is the offset of the l3 register. */ + uint32_t l3; + /** This is the offset of the l4 register. */ + uint32_t l4; + /** This is the offset of the l5 register. */ + uint32_t l5; + /** This is the offset of the l6 register. */ + uint32_t l6; + /** This is the offset of the l7 register. */ + uint32_t l7; + /** This is the offset of the l0 register. */ + uint32_t i0; + /** This is the offset of the i1 register. */ + uint32_t i1; + /** This is the offset of the i2 register. */ + uint32_t i2; + /** This is the offset of the i3 register. */ + uint32_t i3; + /** This is the offset of the i4 register. */ + uint32_t i4; + /** This is the offset of the i5 register. */ + uint32_t i5; + /** This is the offset of the i6 register. */ + uint32_t i6_fp; + /** This is the offset of the i7 register. */ + uint32_t i7; + /** This is the offset of the register used to return structures. */ + void *structure_return_address; + + /* + * The following are for the callee to save the register arguments in + * should this be necessary. + */ + /** This is the offset of the register for saved argument 0. */ + uint32_t saved_arg0; + /** This is the offset of the register for saved argument 1. */ + uint32_t saved_arg1; + /** This is the offset of the register for saved argument 2. */ + uint32_t saved_arg2; + /** This is the offset of the register for saved argument 3. */ + uint32_t saved_arg3; + /** This is the offset of the register for saved argument 4. */ + uint32_t saved_arg4; + /** This is the offset of the register for saved argument 5. */ + uint32_t saved_arg5; + /** This field pads the structure so ldd and std instructions can be used. */ + uint32_t pad0; +} CPU_Minimum_stack_frame; + +#endif /* ASM */ + +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L0_OFFSET 0x00 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L1_OFFSET 0x04 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L2_OFFSET 0x08 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L3_OFFSET 0x0c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L4_OFFSET 0x10 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L5_OFFSET 0x14 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L6_OFFSET 0x18 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L7_OFFSET 0x1c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I0_OFFSET 0x20 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I1_OFFSET 0x24 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I2_OFFSET 0x28 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I3_OFFSET 0x2c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I4_OFFSET 0x30 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I5_OFFSET 0x34 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I7_OFFSET 0x3c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c + +/** This defines the size of the minimum stack frame. */ +#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 + +#define CPU_PER_CPU_CONTROL_SIZE 4 + +/** + * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field + * relative to the Per_CPU_Control begin. + */ +#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0 + +/** + * @defgroup Contexts SPARC Context Structures + * + * @ingroup Score + * + * Generally there are 2 types of context to save. + * + Interrupt registers to save + * + Task level registers to save + * + * This means we have the following 3 context items: + * + task level context stuff:: Context_Control + * + floating point task stuff:: Context_Control_fp + * + special interrupt level context :: Context_Control_interrupt + * + * On the SPARC, we are relatively conservative in that we save most + * of the CPU state in the context area. The ET (enable trap) bit and + * the CWP (current window pointer) fields of the PSR are considered + * system wide resources and are not maintained on a per-thread basis. + */ +/**@{**/ + +#ifndef ASM + +typedef struct { + /** + * This flag is context switched with each thread. It indicates + * that THIS thread has an _ISR_Dispatch stack frame on its stack. + * By using this flag, we can avoid nesting more interrupt dispatching + * attempts on a previously interrupted thread's stack. + */ + uint32_t isr_dispatch_disable; +} CPU_Per_CPU_control; + +/** + * @brief SPARC basic context. + * + * This structure defines the non-volatile integer and processor state context + * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY + * INTERFACE - SPARC Processor Supplement", Third Edition. + * + * The registers g2 through g4 are reserved for applications. GCC uses them as + * volatile registers by default. So they are treated like volatile registers + * in RTEMS as well. + * + * The register g6 contains the per-CPU control of the current processor. It + * is an invariant of the processor context. This register must not be saved + * and restored during context switches or interrupt services. + */ +typedef struct { + /** This will contain the contents of the g5 register. */ + uint32_t g5; + /** This will contain the contents of the g7 register. */ + uint32_t g7; + + /** + * This will contain the contents of the l0 and l1 registers. + * + * Using a double l0_and_l1 will put everything in this structure on a double + * word boundary which allows us to use double word loads and stores safely + * in the context switch. + */ + double l0_and_l1; + /** This will contain the contents of the l2 register. */ + uint32_t l2; + /** This will contain the contents of the l3 register. */ + uint32_t l3; + /** This will contain the contents of the l4 register. */ + uint32_t l4; + /** This will contain the contents of the l5 registeer.*/ + uint32_t l5; + /** This will contain the contents of the l6 register. */ + uint32_t l6; + /** This will contain the contents of the l7 register. */ + uint32_t l7; + + /** This will contain the contents of the i0 register. */ + uint32_t i0; + /** This will contain the contents of the i1 register. */ + uint32_t i1; + /** This will contain the contents of the i2 register. */ + uint32_t i2; + /** This will contain the contents of the i3 register. */ + uint32_t i3; + /** This will contain the contents of the i4 register. */ + uint32_t i4; + /** This will contain the contents of the i5 register. */ + uint32_t i5; + /** This will contain the contents of the i6 (e.g. frame pointer) register. */ + uint32_t i6_fp; + /** This will contain the contents of the i7 register. */ + uint32_t i7; + + /** This will contain the contents of the o6 (e.g. frame pointer) register. */ + uint32_t o6_sp; + /** + * This will contain the contents of the o7 (e.g. address of CALL + * instruction) register. + */ + uint32_t o7; + + /** This will contain the contents of the processor status register. */ + uint32_t psr; + /** + * This field is used to prevent heavy nesting of calls to _Thread_Dispatch + * on an interrupted task's stack. This is problematic on the slower + * SPARC CPU models at high interrupt rates. + */ + uint32_t isr_dispatch_disable; + +#if defined(RTEMS_SMP) + volatile uint32_t is_executing; +#endif +} Context_Control; + +/** + * This macro provides a CPU independent way for RTEMS to access the + * stack pointer in a context structure. The actual name and offset is + * CPU architecture dependent. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->o6_sp + +#ifdef RTEMS_SMP + static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context + ) + { + return context->is_executing; + } + + static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing + ) + { + context->is_executing = is_executing; + } +#endif + +#endif /* ASM */ + +/* + * Offsets of fields with Context_Control for assembly routines. + */ + +/** This macro defines an offset into the context for use in assembly. */ +#define G5_OFFSET 0x00 +/** This macro defines an offset into the context for use in assembly. */ +#define G7_OFFSET 0x04 + +/** This macro defines an offset into the context for use in assembly. */ +#define L0_OFFSET 0x08 +/** This macro defines an offset into the context for use in assembly. */ +#define L1_OFFSET 0x0C +/** This macro defines an offset into the context for use in assembly. */ +#define L2_OFFSET 0x10 +/** This macro defines an offset into the context for use in assembly. */ +#define L3_OFFSET 0x14 +/** This macro defines an offset into the context for use in assembly. */ +#define L4_OFFSET 0x18 +/** This macro defines an offset into the context for use in assembly. */ +#define L5_OFFSET 0x1C +/** This macro defines an offset into the context for use in assembly. */ +#define L6_OFFSET 0x20 +/** This macro defines an offset into the context for use in assembly. */ +#define L7_OFFSET 0x24 + +/** This macro defines an offset into the context for use in assembly. */ +#define I0_OFFSET 0x28 +/** This macro defines an offset into the context for use in assembly. */ +#define I1_OFFSET 0x2C +/** This macro defines an offset into the context for use in assembly. */ +#define I2_OFFSET 0x30 +/** This macro defines an offset into the context for use in assembly. */ +#define I3_OFFSET 0x34 +/** This macro defines an offset into the context for use in assembly. */ +#define I4_OFFSET 0x38 +/** This macro defines an offset into the context for use in assembly. */ +#define I5_OFFSET 0x3C +/** This macro defines an offset into the context for use in assembly. */ +#define I6_FP_OFFSET 0x40 +/** This macro defines an offset into the context for use in assembly. */ +#define I7_OFFSET 0x44 + +/** This macro defines an offset into the context for use in assembly. */ +#define O6_SP_OFFSET 0x48 +/** This macro defines an offset into the context for use in assembly. */ +#define O7_OFFSET 0x4C + +/** This macro defines an offset into the context for use in assembly. */ +#define PSR_OFFSET 0x50 +/** This macro defines an offset into the context for use in assembly. */ +#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 + +#if defined(RTEMS_SMP) + #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 +#endif + +/** This defines the size of the context area for use in assembly. */ +#define CONTEXT_CONTROL_SIZE 0x68 + +#ifndef ASM +/** + * @brief SPARC basic context. + * + * This structure defines floating point context area. + */ +typedef struct { + /** This will contain the contents of the f0 and f1 register. */ + double f0_f1; + /** This will contain the contents of the f2 and f3 register. */ + double f2_f3; + /** This will contain the contents of the f4 and f5 register. */ + double f4_f5; + /** This will contain the contents of the f6 and f7 register. */ + double f6_f7; + /** This will contain the contents of the f8 and f9 register. */ + double f8_f9; + /** This will contain the contents of the f10 and f11 register. */ + double f10_f11; + /** This will contain the contents of the f12 and f13 register. */ + double f12_f13; + /** This will contain the contents of the f14 and f15 register. */ + double f14_f15; + /** This will contain the contents of the f16 and f17 register. */ + double f16_f17; + /** This will contain the contents of the f18 and f19 register. */ + double f18_f19; + /** This will contain the contents of the f20 and f21 register. */ + double f20_f21; + /** This will contain the contents of the f22 and f23 register. */ + double f22_f23; + /** This will contain the contents of the f24 and f25 register. */ + double f24_f25; + /** This will contain the contents of the f26 and f27 register. */ + double f26_f27; + /** This will contain the contents of the f28 and f29 register. */ + double f28_f29; + /** This will contain the contents of the f30 and f31 register. */ + double f30_f31; + /** This will contain the contents of the floating point status register. */ + uint32_t fsr; +} Context_Control_fp; + +#endif /* ASM */ + +/* + * Offsets of fields with Context_Control_fp for assembly routines. + */ + +/** This macro defines an offset into the FPU context for use in assembly. */ +#define FO_F1_OFFSET 0x00 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F2_F3_OFFSET 0x08 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F4_F5_OFFSET 0x10 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F6_F7_OFFSET 0x18 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F8_F9_OFFSET 0x20 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F1O_F11_OFFSET 0x28 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F12_F13_OFFSET 0x30 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F14_F15_OFFSET 0x38 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F16_F17_OFFSET 0x40 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F18_F19_OFFSET 0x48 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F2O_F21_OFFSET 0x50 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F22_F23_OFFSET 0x58 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F24_F25_OFFSET 0x60 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F26_F27_OFFSET 0x68 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F28_F29_OFFSET 0x70 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F3O_F31_OFFSET 0x78 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define FSR_OFFSET 0x80 + +/** This defines the size of the FPU context area for use in assembly. */ +#define CONTEXT_CONTROL_FP_SIZE 0x84 + +#ifndef ASM + +/** @} */ + +/** + * @brief Interrupt stack frame (ISF). + * + * Context saved on stack for an interrupt. + * + * NOTE: The PSR, PC, and NPC are only saved in this structure for the + * benefit of the user's handler. + */ +typedef struct { + /** On an interrupt, we must save the minimum stack frame. */ + CPU_Minimum_stack_frame Stack_frame; + /** This is the offset of the PSR on an ISF. */ + uint32_t psr; + /** This is the offset of the XXX on an ISF. */ + uint32_t pc; + /** This is the offset of the XXX on an ISF. */ + uint32_t npc; + /** This is the offset of the g1 register on an ISF. */ + uint32_t g1; + /** This is the offset of the g2 register on an ISF. */ + uint32_t g2; + /** This is the offset of the g3 register on an ISF. */ + uint32_t g3; + /** This is the offset of the g4 register on an ISF. */ + uint32_t g4; + /** This is the offset of the g5 register on an ISF. */ + uint32_t g5; + /** This is the offset is reserved for alignment on an ISF. */ + uint32_t reserved_for_alignment; + /** This is the offset of the g7 register on an ISF. */ + uint32_t g7; + /** This is the offset of the i0 register on an ISF. */ + uint32_t i0; + /** This is the offset of the i1 register on an ISF. */ + uint32_t i1; + /** This is the offset of the i2 register on an ISF. */ + uint32_t i2; + /** This is the offset of the i3 register on an ISF. */ + uint32_t i3; + /** This is the offset of the i4 register on an ISF. */ + uint32_t i4; + /** This is the offset of the i5 register on an ISF. */ + uint32_t i5; + /** This is the offset of the i6 register on an ISF. */ + uint32_t i6_fp; + /** This is the offset of the i7 register on an ISF. */ + uint32_t i7; + /** This is the offset of the y register on an ISF. */ + uint32_t y; + /** This is the offset of the tpc register on an ISF. */ + uint32_t tpc; +} CPU_Interrupt_frame; + +#endif /* ASM */ + +/* + * Offsets of fields with CPU_Interrupt_frame for assembly routines. + */ + +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_STACK_FRAME_OFFSET 0x00 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c + +/** This defines the size of the ISF area for use in assembly. */ +#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \ + CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 + +#ifndef ASM +/** + * This variable is contains the initialize context for the FP unit. + * It is filled in by _CPU_Initialize and copied into the task's FP + * context area during _CPU_Context_Initialize. + */ +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; + +/** + * The following type defines an entry in the SPARC's trap table. + * + * NOTE: The instructions chosen are RTEMS dependent although one is + * obligated to use two of the four instructions to perform a + * long jump. The other instructions load one register with the + * trap type (a.k.a. vector) and another with the psr. + */ +typedef struct { + /** This will contain a "mov %psr, %l0" instruction. */ + uint32_t mov_psr_l0; + /** This will contain a "sethi %hi(_handler), %l4" instruction. */ + uint32_t sethi_of_handler_to_l4; + /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ + uint32_t jmp_to_low_of_handler_plus_l4; + /** This will contain a " mov _vector, %l3" instruction. */ + uint32_t mov_vector_l3; +} CPU_Trap_table_entry; + +/** + * This is the set of opcodes for the instructions loaded into a trap + * table entry. The routine which installs a handler is responsible + * for filling in the fields for the _handler address and the _vector + * trap type. + * + * The constants following this structure are masks for the fields which + * must be filled in when the handler is installed. + */ +extern const CPU_Trap_table_entry _CPU_Trap_slot_template; + +/** + * The size of the floating point context area. + */ +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +#endif + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 + +/** + * This defines the number of entries in the ISR_Vector_table managed + * by the executive. + * + * On the SPARC, there are really only 256 vectors. However, the executive + * has no easy, fast, reliable way to determine which traps are synchronous + * and which are asynchronous. By default, synchronous traps return to the + * instruction which caused the interrupt. So if you install a software + * trap handler as an executive interrupt handler (which is desirable since + * RTEMS takes care of window and register issues), then the executive needs + * to know that the return address is to the trap rather than the instruction + * following the trap. + * + * So vectors 0 through 255 are treated as regular asynchronous traps which + * provide the "correct" return address. Vectors 256 through 512 are assumed + * by the executive to be synchronous and to require that the return address + * be fudged. + * + * If you use this mechanism to install a trap handler which must reexecute + * the instruction which caused the trap, then it should be installed as + * an asynchronous trap. This will avoid the executive changing the return + * address. + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 + +/** + * The SPARC has 256 vectors but the port treats 256-512 as synchronous + * traps. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 + +/** + * This is the bit step in a vector number to indicate it is being installed + * as a synchronous trap. + */ +#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 + +/** + * This macro indicates that @a _trap as an asynchronous trap. + */ +#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) + +/** + * This macro indicates that @a _trap as a synchronous trap. + */ +#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) + +/** + * This macro returns the real hardware vector number associated with @a _trap. + */ +#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) + +/** + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** + * Should be large enough to run all tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * This appears to be a fairly generous number for the SPARC since + * represents a call depth of about 20 routines based on the minimum + * stack frame. + */ +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +/** + * What is the size of a pointer on this architecture? + */ +#define CPU_SIZEOF_POINTER 4 + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * On the SPARC, this is required for double word loads and stores. + */ +#define CPU_ALIGNMENT 8 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * + * The alignment restrictions for the SPARC are not that strict but this + * should unsure that the stack is always sufficiently alignment that the + * window overflow, underflow, and flush routines can use double word loads + * and stores. + */ +#define CPU_STACK_ALIGNMENT 16 + +#ifndef ASM + +/* + * ISR handler macros + */ + +/** + * Support routine to initialize the RTEMS vector table after it is allocated. + */ +#define _CPU_Initialize_vectors() + +/** + * Disable all interrupts for a critical section. The previous + * level is returned in _level. + */ +#define _CPU_ISR_Disable( _level ) \ + (_level) = sparc_disable_interrupts() + +/** + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of a critical section. The parameter + * _level is not modified. + */ +#define _CPU_ISR_Enable( _level ) \ + sparc_enable_interrupts( _level ) + +/** + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long critical + * sections into two or more parts. The parameter _level is not + * modified. + */ +#define _CPU_ISR_Flash( _level ) \ + sparc_flash_interrupts( _level ) + +/** + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a straight fashion are undefined. + */ +#define _CPU_ISR_Set_level( _newlevel ) \ + sparc_enable_interrupts( _newlevel << 8) + +/** + * @brief Obtain the current interrupt disable level. + * + * This method is invoked to return the current interrupt disable level. + * + * @return This method returns the current interrupt disable level. + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/** + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * @param[in] the_context points to the context area + * @param[in] stack_base is the low address of the allocated stack area + * @param[in] size is the size of the stack area in bytes + * @param[in] new_level is the interrupt level for the task + * @param[in] entry_point is the task's entry point + * @param[in] is_fp is set to TRUE if the task is a floating point task + * @param[in] tls_area is the thread-local storage (TLS) area + * + * NOTE: Implemented as a subroutine for the SPARC port. + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + +/** + * This macro is invoked from _Thread_Handler to do whatever CPU + * specific magic is required that must be done in the context of + * the thread when it starts. + * + * On the SPARC, this is setting the frame pointer so GDB is happy. + * Make GDB stop unwinding at _Thread_Handler, previous register window + * Frame pointer is 0 and calling address must be a function with starting + * with a SAVE instruction. If return address is leaf-function (no SAVE) + * GDB will not look at prev reg window fp. + * + * _Thread_Handler is known to start with SAVE. + */ +#define _CPU_Context_Initialization_at_thread_begin() \ + do { \ + __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ + } while (0) + +/** + * This routine is responsible for somehow restarting the currently + * executing task. + * + * On the SPARC, this is is relatively painless but requires a small + * amount of wrapper code before using the regular restore code in + * of the context switch. + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/** + * The FP context area for the SPARC is a simple structure and nothing + * special is required to find the "starting load point" + */ +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +/** + * This routine initializes the FP context area passed to it to. + * + * The SPARC allows us to use the simple initialization model + * in which an "initial" FP context was saved into _CPU_Null_fp_context + * at CPU initialization and it is simply copied into the destination + * context. + */ +#define _CPU_Context_Initialize_fp( _destination ) \ + do { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } while (0) + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + */ +extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +#if ( SPARC_HAS_BITSCAN == 0 ) + /** + * The SPARC port uses the generic C algorithm for bitfield scan if the + * CPU model does not have a scan instruction. + */ + #define CPU_USE_GENERIC_BITFIELD_CODE TRUE + /** + * The SPARC port uses the generic C algorithm for bitfield scan if the + * CPU model does not have a scan instruction. Thus is needs the generic + * data table used by that algorithm. + */ + #define CPU_USE_GENERIC_BITFIELD_DATA TRUE +#else + #error "scan instruction not currently supported by RTEMS!!" +#endif + +/* end of Bitfield handler macros */ + +/* functions */ + +/** + * @brief SPARC specific initialization. + * + * This routine performs CPU dependent initialization. + */ +void _CPU_Initialize(void); + +/** + * @brief SPARC specific raw ISR installer. + * + * This routine installs @a new_handler to be directly called from the trap + * table. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the new ISR handler + * @param[in] old_handler will contain the old ISR handler + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @brief SPARC specific RTEMS ISR installer. + * + * This routine installs an interrupt vector. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the new ISR handler + * @param[in] old_handler will contain the old ISR handler + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @brief SPARC specific context switch. + * + * This routine switches from the run context to the heir context. + * + * @param[in] run is the currently executing thread + * @param[in] heir will become the currently executing thread + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * @brief SPARC specific context restore. + * + * This routine is generally used only to restart self in an + * efficient manner. + * + * @param[in] new_context is the context to restore + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + +/** + * @brief The pointer to the current per-CPU control is available via register + * g6. + */ +register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); + +#define _CPU_Get_current_per_CPU_control() ( _SPARC_Per_CPU_current ) + +#if defined(RTEMS_SMP) + uint32_t _CPU_SMP_Initialize( void ); + + bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + + void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + + #if defined(__leon__) && !defined(RTEMS_PARAVIRT) + static inline uint32_t _CPU_SMP_Get_current_processor( void ) + { + return _LEON3_Get_current_processor(); + } + #else + uint32_t _CPU_SMP_Get_current_processor( void ); + #endif + + void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + + #if defined(__leon__) + void _LEON3_Start_multitasking( Context_Control *heir ) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + #define _CPU_Start_multitasking _LEON3_Start_multitasking + #endif + + static inline void _CPU_SMP_Processor_event_broadcast( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + static inline void _CPU_SMP_Processor_event_receive( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } +#endif + +/** + * @brief SPARC specific save FPU method. + * + * This routine saves the floating point context passed to it. + * + * @param[in] fp_context_ptr is the area to save into + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/** + * @brief SPARC specific restore FPU method. + * + * This routine restores the floating point context passed to it. + * + * @param[in] fp_context_ptr is the area to restore from + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +typedef struct { + uint32_t trap; + CPU_Interrupt_frame *isf; +} CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/** + * @brief SPARC specific method to endian swap an uint32_t. + * + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * @param[in] value is the value to endian swap + * + * This version will work on any processor, but if you come across a better + * way for the SPARC PLEASE use it. The most common way to swap a 32-bit + * entity as shown below is not any more efficient on the SPARC. + * + * - swap least significant two bytes with 16-bit rotate + * - swap upper and lower 16-bits + * - swap most significant two bytes with 16-bit rotate + * + * It is not obvious how the SPARC can do significantly better than the + * generic code. gcc 2.7.0 only generates about 12 instructions for the + * following code at optimization level four (i.e. -O4). + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +/** + * @brief SPARC specific method to endian swap an uint16_t. + * + * The following routine swaps the endian format of a uint16_t. + * + * @param[in] value is the value to endian swap + */ +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +typedef CPU_Counter_ticks (*SPARC_Counter_difference)( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +/* + * The SPARC processors supported by RTEMS have no built-in CPU counter + * support. We have to use some hardware counter module for this purpose. The + * BSP must provide a 32-bit register which contains the current CPU counter + * value and a function for the difference calculation. It can use for example + * the GPTIMER instance used for the clock driver. + */ +typedef struct { + volatile const CPU_Counter_ticks *counter_register; + SPARC_Counter_difference counter_difference; +} SPARC_Counter; + +extern SPARC_Counter _SPARC_Counter; + +/* + * Returns always a value of one regardless of the parameters. This prevents + * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe + * default. + */ +CPU_Counter_ticks _SPARC_Counter_difference_default( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +static inline bool _SPARC_Counter_is_default( void ) +{ + return _SPARC_Counter.counter_difference + == _SPARC_Counter_difference_default; +} + +static inline void _SPARC_Counter_initialize( + volatile const CPU_Counter_ticks *counter_register, + SPARC_Counter_difference counter_difference +) +{ + _SPARC_Counter.counter_register = counter_register; + _SPARC_Counter.counter_difference = counter_difference; +} + +static inline CPU_Counter_ticks _CPU_Counter_read( void ) +{ + return *_SPARC_Counter.counter_register; +} + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return (*_SPARC_Counter.counter_difference)( second, first ); +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/sparc/erc32/rtems/score/cpuatomic.h b/include/sparc/erc32/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..6021d1c3f4 --- /dev/null +++ b/include/sparc/erc32/rtems/score/cpuatomic.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/rtems/score/cpuatomic.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/rtems/score/cpuatomic.h> diff --git a/include/sparc/erc32/rtems/score/types.h b/include/sparc/erc32/rtems/score/types.h new file mode 100644 index 0000000000..71a401c454 --- /dev/null +++ b/include/sparc/erc32/rtems/score/types.h @@ -0,0 +1,59 @@ +/** + * @file + * + * @brief SPARC CPU Type Definitions + * + * This include file contains type definitions pertaining to the + * SPARC processor family. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include <rtems/score/basedefs.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Priority bit map type. + * + * On the SPARC, there is no bitscan instruction and no penalty associated + * for using 16-bit variables. With no overriding architectural factors, + * just using a uint16_t. + */ +typedef uint16_t Priority_bit_map_Word; + +/** + * @brief SPARC ISR handler return type. + * + * This is the type which SPARC ISR Handlers return. + */ +typedef void sparc_isr; + +/** + * @brief SPARC ISR handler prototype. + * + * This is the prototype for SPARC ISR Handlers. + */ +typedef void ( *sparc_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/include/sparc/erc32/tm27.h b/include/sparc/erc32/tm27.h new file mode 100644 index 0000000000..958036fbf0 --- /dev/null +++ b/include/sparc/erc32/tm27.h @@ -0,0 +1,85 @@ +/** + * @file + * @ingroup sparc_erc32 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * COPYRIGHT (c) 2006. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Since the interrupt code for the SPARC supports both synchronous + * and asynchronous trap handlers, support for testing with both + * is included. + */ + +#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0 + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1) + +#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); + +#define Cause_tm27_intr() \ + __asm__ volatile( "ta 0x10; nop " ); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/* + * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. + */ + +#else /* use a regular asynchronous trap */ + +#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1 +#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1) +#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) +#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); \ + set_vector( (handler), TEST_VECTOR2, 1 ); + +#define Cause_tm27_intr() \ + do { \ + ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \ + nop(); \ + nop(); \ + nop(); \ + } while (0) + +#define Clear_tm27_intr() \ + ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE ) + +#define Lower_tm27_intr() /* empty */ + +#endif + +#endif diff --git a/include/sparc/leon2/bsp.h b/include/sparc/leon2/bsp.h new file mode 100644 index 0000000000..41a1e43629 --- /dev/null +++ b/include/sparc/leon2/bsp.h @@ -0,0 +1,214 @@ +/** + * @file + * + * @ingroup sparc_leon2 + * + * @brief Global BSP Definitions. + */ + +/* bsp.h + * + * This include file contains all SPARC simulator definitions. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to ERC32 implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef _BSP_H +#define _BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <leon.h> +#include <rtems/clockdrv.h> +#include <rtems/console.h> +#include <rtems/irq-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sparc_leon2 LEON2 Support + * + * @ingroup bsp_sparc + * + * @brief LEON2 Support Package + * + */ + +/* SPARC CPU variant: LEON2 */ +#define LEON2 1 + +/* + * BSP provides its own Idle thread body + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_leon_open_eth_driver_attach( + struct rtems_bsdnet_ifconfig *config +); +extern int rtems_smc91111_driver_attach_leon2( + struct rtems_bsdnet_ifconfig *config +); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "open_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ + rtems_leon_open_eth_driver_attach +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ + rtems_smc91111_driver_attach_leon2 + +#define HAS_SMC91111 + +/* Configure GRETH driver */ +#define GRETH_SUPPORTED +#define GRETH_MEM_LOAD(addr) leon_r32_no_cache((uintptr_t) addr) + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +extern int CPU_SPARC_HAS_SNOOPING; + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; + +extern int end; /* last address in the program */ + +/* miscellaneous stuff assumed to exist */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +void BSP_fatal_exit(uint32_t error); + +void bsp_spurious_initialize( void ); + +/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function + * can be called at any time. The work-area will shrink when called before + * bsp_work_area_initialize(). malloc() is called to get memory when this + * function is called after bsp_work_area_initialize(). + */ +void *bsp_early_malloc(int size); + +/* Interrupt Service Routine (ISR) pointer */ +typedef void (*bsp_shared_isr)(void *arg); + +/* Initializes the Shared System Interrupt service */ +extern void BSP_shared_interrupt_init(void); + +/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple + * interrupt handlers may use the same IRQ number, all ISRs will be called + * when an interrupt on that line is fired. + * + * Arguments + * irq System IRQ number + * info Optional Name of IRQ source + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_register + ( + int irq, + const char *info, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_install(irq, info, + RTEMS_INTERRUPT_SHARED, isr, arg); +} + +/* Unregister previously registered shared IRQ handler. + * + * Arguments + * irq System IRQ number + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_unregister + ( + int irq, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_remove(irq, isr, arg); +} + +/* Clear interrupt pending on IRQ controller, this is typically done on a + * level triggered interrupt source such as PCI to avoid taking double IRQs. + * In such a case the interrupt source must be cleared first on LEON, before + * acknowledging the IRQ with this function. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_clear(int irq); + +/* Enable Interrupt. This function will unmask the IRQ at the interrupt + * controller. This is normally done by _register(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_unmask(int irq); + +/* Disable Interrupt. This function will mask one IRQ at the interrupt + * controller. This is normally done by _unregister(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_mask(int irq); + +/* + * Delay method + */ +void rtems_bsp_delay(int usecs); + +/* + * Prototypes for BSP methods that are used across file boundaries + */ +int cchip1_register(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/sparc/leon2/bsp/irq.h b/include/sparc/leon2/bsp/irq.h new file mode 100644 index 0000000000..086bf253c4 --- /dev/null +++ b/include/sparc/leon2/bsp/irq.h @@ -0,0 +1,28 @@ +/** + * @file + * @ingroup sparc_leon2 + * @brief Interrupts definitions + * + * Based on libbsp/shared/include/irq.h. + */ + +/* + * Copyright (c) 2012. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_LEON2_IRQ_CONFIG_H +#define LIBBSP_LEON2_IRQ_CONFIG_H + +#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD + +/* No extra check is needed */ +#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR + +#endif /* LIBBSP_LEON2_IRQ_CONFIG_H */ diff --git a/include/sparc/leon2/coverhd.h b/include/sparc/leon2/coverhd.h new file mode 100644 index 0000000000..51037e4129 --- /dev/null +++ b/include/sparc/leon2/coverhd.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/coverhd.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/coverhd.h> diff --git a/include/sparc/leon2/leon.h b/include/sparc/leon2/leon.h new file mode 100644 index 0000000000..7ec6b1dcf9 --- /dev/null +++ b/include/sparc/leon2/leon.h @@ -0,0 +1,423 @@ +/** + * @defgroup leon1 Leon-1 Handler + * @ingroup sparc_leon2 + * + * @file + * @ingroup leon1 + * @brief Handlers Leon-1 + * + * This include file contains information pertaining to the LEON-1. + * The LEON-1 is a custom SPARC V7 implementation. + * This CPU has a number of on-board peripherals and + * was developed by the European Space Agency to target space applications. + * + * NOTE: Other than where absolutely required, this version currently + * supports only the peripherals and bits used by the basic board + * support package. This includes at least significant pieces of + * the following items: + * + * + UART Channels A and B + * + Real Time Clock + * + Memory Control Register + * + Interrupt Control + * + */ + +/* + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to LEON implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef _INCLUDE_LEON_h +#define _INCLUDE_LEON_h + +#include <rtems/score/sparc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Interrupt Sources + * + * The interrupt source numbers directly map to the trap type and to + * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + */ + +#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 +#define LEON_INTERRUPT_UART_2_RX_TX 2 +#define LEON_INTERRUPT_UART_1_RX_TX 3 +#define LEON_INTERRUPT_EXTERNAL_0 4 +#define LEON_INTERRUPT_EXTERNAL_1 5 +#define LEON_INTERRUPT_EXTERNAL_2 6 +#define LEON_INTERRUPT_EXTERNAL_3 7 +#define LEON_INTERRUPT_TIMER1 8 +#define LEON_INTERRUPT_TIMER2 9 +#define LEON_INTERRUPT_EMPTY1 10 +#define LEON_INTERRUPT_EMPTY2 11 +#define LEON_INTERRUPT_EMPTY3 12 +#define LEON_INTERRUPT_EMPTY4 13 +#define LEON_INTERRUPT_EMPTY5 14 +#define LEON_INTERRUPT_EMPTY6 15 + +#ifndef ASM + +/* + * Trap Types for on-chip peripherals + * + * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments + * + * NOTE: The priority level for each source corresponds to the least + * significant nibble of the trap type. + */ + +#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) + +#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) + +#define LEON_INT_TRAP( _trap ) \ + ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \ + (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) ) + +/* + * Structure for LEON memory mapped registers. + * + * Source: Section 6.1 - On-chip registers + * + * NOTE: There is only one of these structures per CPU, its base address + * is 0x80000000, and the variable LEON_REG is placed there by the + * linkcmds file. + */ + +typedef struct { + volatile unsigned int Memory_Config_1; + volatile unsigned int Memory_Config_2; + volatile unsigned int Edac_Control; + volatile unsigned int Failed_Address; + volatile unsigned int Memory_Status; + volatile unsigned int Cache_Control; + volatile unsigned int Power_Down; + volatile unsigned int Write_Protection_1; + volatile unsigned int Write_Protection_2; + volatile unsigned int Leon_Configuration; + volatile unsigned int dummy2; + volatile unsigned int dummy3; + volatile unsigned int dummy4; + volatile unsigned int dummy5; + volatile unsigned int dummy6; + volatile unsigned int dummy7; + volatile unsigned int Timer_Counter_1; + volatile unsigned int Timer_Reload_1; + volatile unsigned int Timer_Control_1; + volatile unsigned int Watchdog; + volatile unsigned int Timer_Counter_2; + volatile unsigned int Timer_Reload_2; + volatile unsigned int Timer_Control_2; + volatile unsigned int dummy8; + volatile unsigned int Scaler_Counter; + volatile unsigned int Scaler_Reload; + volatile unsigned int dummy9; + volatile unsigned int dummy10; + volatile unsigned int UART_Channel_1; + volatile unsigned int UART_Status_1; + volatile unsigned int UART_Control_1; + volatile unsigned int UART_Scaler_1; + volatile unsigned int UART_Channel_2; + volatile unsigned int UART_Status_2; + volatile unsigned int UART_Control_2; + volatile unsigned int UART_Scaler_2; + volatile unsigned int Interrupt_Mask; + volatile unsigned int Interrupt_Pending; + volatile unsigned int Interrupt_Force; + volatile unsigned int Interrupt_Clear; + volatile unsigned int PIO_Data; + volatile unsigned int PIO_Direction; + volatile unsigned int PIO_Interrupt; +} LEON_Register_Map; + +#endif + +/* + * The following constants are intended to be used ONLY in assembly + * language files. + * + * NOTE: The intended style of usage is to load the address of LEON REGS + * into a register and then use these as displacements from + * that register. + */ + +#ifdef ASM + +#define LEON_REG_MEMCFG1_OFFSET 0x00 +#define LEON_REG_MEMCFG2_OFFSET 0x04 +#define LEON_REG_EDACCTRL_OFFSET 0x08 +#define LEON_REG_FAILADDR_OFFSET 0x0C +#define LEON_REG_MEMSTATUS_OFFSET 0x10 +#define LEON_REG_CACHECTRL_OFFSET 0x14 +#define LEON_REG_POWERDOWN_OFFSET 0x18 +#define LEON_REG_WRITEPROT1_OFFSET 0x1C +#define LEON_REG_WRITEPROT2_OFFSET 0x20 +#define LEON_REG_LEONCONF_OFFSET 0x24 +#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28 +#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C +#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30 +#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34 +#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38 +#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C +#define LEON_REG_TIMERCNT1_OFFSET 0x40 +#define LEON_REG_TIMERLOAD1_OFFSET 0x44 +#define LEON_REG_TIMERCTRL1_OFFSET 0x48 +#define LEON_REG_WDOG_OFFSET 0x4C +#define LEON_REG_TIMERCNT2_OFFSET 0x50 +#define LEON_REG_TIMERLOAD2_OFFSET 0x54 +#define LEON_REG_TIMERCTRL2_OFFSET 0x58 +#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C +#define LEON_REG_SCALERCNT_OFFSET 0x60 +#define LEON_REG_SCALER_LOAD_OFFSET 0x64 +#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68 +#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C +#define LEON_REG_UARTDATA1_OFFSET 0x70 +#define LEON_REG_UARTSTATUS1_OFFSET 0x74 +#define LEON_REG_UARTCTRL1_OFFSET 0x78 +#define LEON_REG_UARTSCALER1_OFFSET 0x7C +#define LEON_REG_UARTDATA2_OFFSET 0x80 +#define LEON_REG_UARTSTATUS2_OFFSET 0x84 +#define LEON_REG_UARTCTRL2_OFFSET 0x88 +#define LEON_REG_UARTSCALER2_OFFSET 0x8C +#define LEON_REG_IRQMASK_OFFSET 0x90 +#define LEON_REG_IRQPEND_OFFSET 0x94 +#define LEON_REG_IRQFORCE_OFFSET 0x98 +#define LEON_REG_IRQCLEAR_OFFSET 0x9C +#define LEON_REG_PIODATA_OFFSET 0xA0 +#define LEON_REG_PIODIR_OFFSET 0xA4 +#define LEON_REG_PIOIRQ_OFFSET 0xA8 +#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4 +#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8 + +#endif + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 + + +/* + * The following defines the bits in the Timer Control Register. + */ + +#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ + /* 0 = no function */ + +/* + * The following defines the bits in the UART Control Registers. + * + */ + +#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ + +/* + * The following defines the bits in the LEON UART Status Registers. + */ + +#define LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */ +#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ +#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ +#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ +#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ +#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ +#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ +#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ +#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ + + +/* + * The following defines the bits in the LEON UART Status Registers. + */ + +#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ +#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ +#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ +#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ +#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ +#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ +#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ +#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ + +#ifndef ASM + +/* + * This is used to manipulate the on-chip registers. + * + * The following symbol must be defined in the linkcmds file and point + * to the correct location. + */ + +extern LEON_Register_Map LEON_REG; + +static __inline__ int bsp_irq_fixup(int irq) +{ + return irq; +} + +/* + * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + * + * NOTE: For operations which are not atomic, this code disables interrupts + * to guarantee there are no intervening accesses to the same register. + * The operations which read the register, modify the value and then + * store the result back are vulnerable. + */ + +#define LEON_Clear_interrupt( _source ) \ + do { \ + LEON_REG.Interrupt_Clear = (1 << (_source)); \ + } while (0) + +#define LEON_Force_interrupt( _source ) \ + do { \ + LEON_REG.Interrupt_Force = (1 << (_source)); \ + } while (0) + +#define LEON_Is_interrupt_pending( _source ) \ + (LEON_REG.Interrupt_Pending & (1 << (_source))) + +#define LEON_Is_interrupt_masked( _source ) \ + (!(LEON_REG.Interrupt_Mask & (1 << (_source)))) + +#define LEON_Mask_interrupt( _source ) \ + do { \ + uint32_t _level; \ + \ + _level = sparc_disable_interrupts(); \ + LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define LEON_Unmask_interrupt( _source ) \ + do { \ + uint32_t _level; \ + \ + _level = sparc_disable_interrupts(); \ + LEON_REG.Interrupt_Mask |= (1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define LEON_Disable_interrupt( _source, _previous ) \ + do { \ + uint32_t _level; \ + uint32_t _mask = 1 << (_source); \ + \ + _level = sparc_disable_interrupts(); \ + (_previous) = LEON_REG.Interrupt_Mask; \ + LEON_REG.Interrupt_Mask = _previous & ~_mask; \ + sparc_enable_interrupts( _level ); \ + (_previous) &= _mask; \ + } while (0) + +#define LEON_Restore_interrupt( _source, _previous ) \ + do { \ + uint32_t _level; \ + uint32_t _mask = 1 << (_source); \ + \ + _level = sparc_disable_interrupts(); \ + LEON_REG.Interrupt_Mask = \ + (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +/* Make all SPARC BSPs have common macros for interrupt handling */ +#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) +#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) +#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) +#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) +#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) +#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) +#define BSP_Disable_interrupt(_source, _previous) \ + LEON_Disable_interrupt(_source, _prev) +#define BSP_Restore_interrupt(_source, _previous) \ + LEON_Restore_interrupt(_source, _previous) + +/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ +#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ + BSP_Is_interrupt_masked(_source) +#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ + BSP_Unmask_interrupt(_source) +#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ + BSP_Mask_interrupt(_source) +#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ + BSP_Disable_interrupt(_source, _prev) +#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ + BSP_Cpu_Restore_interrupt(_source, _previous) + +/* + * Each timer control register is organized as follows: + * + * D0 - Enable + * 1 = enable counting + * 0 = hold scaler and counter + * + * D1 - Counter Reload + * 1 = reload counter at zero and restart + * 0 = stop counter at zero + * + * D2 - Counter Load + * 1 = load counter with preset value + * 0 = no function + * + */ + +#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 +#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 + +#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 + +#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 +#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 + +#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 +#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 + +#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 +#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 + +/* Load 32-bit word by forcing a cache-miss */ +static inline unsigned int leon_r32_no_cache(uintptr_t addr) +{ + unsigned int tmp; + __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); + return tmp; +} + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* !_INCLUDE_LEON_h */ + diff --git a/include/sparc/leon2/libcpu/byteorder.h b/include/sparc/leon2/libcpu/byteorder.h new file mode 100644 index 0000000000..9f67cf1c45 --- /dev/null +++ b/include/sparc/leon2/libcpu/byteorder.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/libcpu/byteorder.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/libcpu/byteorder.h> diff --git a/include/sparc/leon2/rtems/asm.h b/include/sparc/leon2/rtems/asm.h new file mode 100644 index 0000000000..5691a127d5 --- /dev/null +++ b/include/sparc/leon2/rtems/asm.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/asm.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/asm.h> diff --git a/include/sparc/leon2/rtems/score/cpu.h b/include/sparc/leon2/rtems/score/cpu.h new file mode 100644 index 0000000000..0c9d359cab --- /dev/null +++ b/include/sparc/leon2/rtems/score/cpu.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/cpu.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/cpu.h> diff --git a/include/sparc/leon2/rtems/score/cpuatomic.h b/include/sparc/leon2/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..6021d1c3f4 --- /dev/null +++ b/include/sparc/leon2/rtems/score/cpuatomic.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/rtems/score/cpuatomic.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/rtems/score/cpuatomic.h> diff --git a/include/sparc/leon2/rtems/score/types.h b/include/sparc/leon2/rtems/score/types.h new file mode 100644 index 0000000000..a6cb6998f4 --- /dev/null +++ b/include/sparc/leon2/rtems/score/types.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/types.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/types.h> diff --git a/include/sparc/leon2/tm27.h b/include/sparc/leon2/tm27.h new file mode 100644 index 0000000000..0d28641b9b --- /dev/null +++ b/include/sparc/leon2/tm27.h @@ -0,0 +1,84 @@ +/** + * @file + * @ingroup sparc_leon2 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * COPYRIGHT (c) 2006. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Since the interrupt code for the SPARC supports both synchronous + * and asynchronous trap handlers, support for testing with both + * is included. + */ + +#define SIS_USE_SYNCHRONOUS_TRAP 0 + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +#if (SIS_USE_SYNCHRONOUS_TRAP == 1) + +#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); + +#define Cause_tm27_intr() \ + __asm__ volatile( "ta 0x10; nop " ); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/* + * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. + */ + +#else /* use a regular asynchronous trap */ + +#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 +#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) +#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 +#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); \ + set_vector( (handler), TEST_VECTOR2, 1 ); + +#define Cause_tm27_intr() \ + do { \ + LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ + nop(); \ + nop(); \ + nop(); \ + } while (0) + +#define Clear_tm27_intr() \ + LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) + +#define Lower_tm27_intr() /* empty */ + +#endif + +#endif diff --git a/include/sparc/leon3/bsp.h b/include/sparc/leon3/bsp.h new file mode 100644 index 0000000000..2514190750 --- /dev/null +++ b/include/sparc/leon3/bsp.h @@ -0,0 +1,248 @@ +/** + * @file + * + * @ingroup sparc_leon3 + * + * @brief Global BSP Definitions. + */ + +/* bsp.h + * + * This include file contains all SPARC simulator definitions. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to ERC32 implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef _BSP_H +#define _BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <leon.h> +#include <rtems/clockdrv.h> +#include <rtems/console.h> +#include <rtems/irq-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sparc_leon3 LEON3 Support + * + * @ingroup bsp_sparc + * + * @brief LEON3 support package + * + */ + +/* SPARC CPU variant: LEON3 */ +#define LEON3 1 + +/* + * BSP provides its own Idle thread body + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* Maximum supported APBUARTs by BSP */ +#define BSP_NUMBER_OF_TERMIOS_PORTS 8 + +/* Make sure maximum number of consoles fit in filesystem */ +#define BSP_MAXIMUM_DEVICES 8 + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_leon_open_eth_driver_attach( + struct rtems_bsdnet_ifconfig *config, + int attach +); +extern int rtems_smc91111_driver_attach_leon3( + struct rtems_bsdnet_ifconfig *config, + int attach +); +extern int rtems_leon_greth_driver_attach( + struct rtems_bsdnet_ifconfig *config, + int attach +); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME_OPENETH "open_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ + rtems_leon_open_eth_driver_attach +#define RTEMS_BSP_NETWORK_DRIVER_NAME_SMC91111 "smc_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ + rtems_smc91111_driver_attach_leon3 +#define RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH "gr_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH \ + rtems_leon_greth_driver_attach + +#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH +#endif + +#define HAS_SMC91111 + +/* Configure GRETH driver */ +#define GRETH_SUPPORTED +#define GRETH_MEM_LOAD(addr) leon_r32_no_cache(addr) + +extern int CPU_SPARC_HAS_SNOOPING; + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; + +extern int end; /* last address in the program */ + +/* miscellaneous stuff assumed to exist */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +void BSP_fatal_exit(uint32_t error); + +void bsp_spurious_initialize( void ); + +/* + * Delay for the specified number of microseconds. + */ +void rtems_bsp_delay(int usecs); + +/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function + * can be called at any time. The work-area will shrink when called before + * bsp_work_area_initialize(). malloc() is called to get memory when this + * function is called after bsp_work_area_initialize(). + */ +void *bsp_early_malloc(int size); + +/* Interrupt Service Routine (ISR) pointer */ +typedef void (*bsp_shared_isr)(void *arg); + +/* Initializes the Shared System Interrupt service */ +extern void BSP_shared_interrupt_init(void); + +/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple + * interrupt handlers may use the same IRQ number, all ISRs will be called + * when an interrupt on that line is fired. + * + * Arguments + * irq System IRQ number + * info Optional Name of IRQ source + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_register + ( + int irq, + const char *info, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_install(irq, info, + RTEMS_INTERRUPT_SHARED, isr, arg); +} + +/* Unregister previously registered shared IRQ handler. + * + * Arguments + * irq System IRQ number + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_unregister + ( + int irq, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_remove(irq, isr, arg); +} + +/* Clear interrupt pending on IRQ controller, this is typically done on a + * level triggered interrupt source such as PCI to avoid taking double IRQs. + * In such a case the interrupt source must be cleared first on LEON, before + * acknowledging the IRQ with this function. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_clear(int irq); + +/* Enable Interrupt. This function will unmask the IRQ at the interrupt + * controller. This is normally done by _register(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_unmask(int irq); + +/* Disable Interrupt. This function will mask one IRQ at the interrupt + * controller. This is normally done by _unregister(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_mask(int irq); + +#if defined(RTEMS_SMP) || defined(RTEMS_MULTIPROCESSING) +/* Irq used by the shared memory driver and for inter-processor interrupts. + * The variable is weakly linked. Redefine the variable in your application + * to override the BSP default. + */ +extern const unsigned char LEON3_mp_irq; +#endif + +#ifdef RTEMS_SMP +/* Weak table used to implement static interrupt CPU affinity in a SMP + * configuration. The array index is the interrupt to be looked up, and + * the array[INTERRUPT] content is the CPU number relative to boot CPU + * index that will be servicing the interrupts from the IRQ source. The + * default is to let the first CPU (the boot cpu) to handle all + * interrupts (all zeros). + */ +extern const unsigned char LEON3_irq_to_cpu[32]; +#endif + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/include/sparc/leon3/bsp/irq.h b/include/sparc/leon3/bsp/irq.h new file mode 100644 index 0000000000..b429c864b5 --- /dev/null +++ b/include/sparc/leon3/bsp/irq.h @@ -0,0 +1,44 @@ +/** + * @file + * @ingroup sparc_leon3 + * @brief LEON3 generic shared IRQ setup + * + * Based on libbsp/shared/include/irq.h. + */ + +/* + * Copyright (c) 2012. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_LEON3_IRQ_CONFIG_H +#define LIBBSP_LEON3_IRQ_CONFIG_H + +#include <leon.h> + +#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ +#define BSP_INTERRUPT_VECTOR_MAX_EXT 31 /* Extended IRQ controller */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_EXT + +/* The check is different depending on IRQ controller, runtime detected */ +#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR + +/** + * @brief Returns true if the interrupt vector with number @a vector is valid. + */ +static inline bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) +{ + return (rtems_vector_number) BSP_INTERRUPT_VECTOR_MIN <= vector + && ((vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_STD && + LEON3_IrqCtrl_EIrq == 0) || + (vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_EXT && + LEON3_IrqCtrl_EIrq != 0)); +} + +#endif /* LIBBSP_LEON3_IRQ_CONFIG_H */ diff --git a/include/sparc/leon3/coverhd.h b/include/sparc/leon3/coverhd.h new file mode 100644 index 0000000000..51037e4129 --- /dev/null +++ b/include/sparc/leon3/coverhd.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/coverhd.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/coverhd.h> diff --git a/include/sparc/leon3/leon.h b/include/sparc/leon3/leon.h new file mode 100644 index 0000000000..c7270cf7d9 --- /dev/null +++ b/include/sparc/leon3/leon.h @@ -0,0 +1,391 @@ +/** + * @file + * @ingroup sparc_leon3 + * @brief LEON3 BSP data types and macros + */ + +/* leon.h + * + * LEON3 BSP data types and macros. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * Modified for LEON3 BSP. + * COPYRIGHT (c) 2004. + * Gaisler Research. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _INCLUDE_LEON_h +#define _INCLUDE_LEON_h + +#include <rtems.h> +#include <amba.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEON_INTERRUPT_EXTERNAL_1 5 + +#ifndef ASM +/* + * Trap Types for on-chip peripherals + * + * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments + * + * NOTE: The priority level for each source corresponds to the least + * significant nibble of the trap type. + */ + +#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) + +#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) + +#define LEON_INT_TRAP( _trap ) \ + ( (_trap) >= 0x11 && \ + (_trap) <= 0x1F ) + +/* /\* */ +/* * This is used to manipulate the on-chip registers. */ +/* * */ +/* * The following symbol must be defined in the linkcmds file and point */ +/* * to the correct location. */ +/* *\/ */ +/* Leon uses dynamic register mapping using amba configuration records */ +/* LEON_Register_Map is obsolete */ +/* extern LEON_Register_Map LEON_REG; */ + +#endif + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 + + +/* + * The following defines the bits in the Timer Control Register. + */ + +#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ + /* 0 = no function */ + +/* + * The following defines the bits in the LEON Cache Control Register. + */ +#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ +#define LEON3_REG_CACHE_CTRL_DS 0x00800000 /* Data cache snooping */ + +/* LEON3 Interrupt Controller */ +extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; +/* LEON3 GP Timer */ +extern volatile struct gptimer_regs *LEON3_Timer_Regs; + +/* LEON3 CPU Index of boot CPU */ +extern uint32_t LEON3_Cpu_Index; + +/* The external IRQ number, -1 if not external interrupts */ +extern int LEON3_IrqCtrl_EIrq; + +static __inline__ int bsp_irq_fixup(int irq) +{ + int eirq, cpu; + + if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { + /* Get interrupt number from IRQ controller */ + cpu = _LEON3_Get_current_processor(); + eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; + if (eirq & 0x10) + irq = eirq; + } + + return irq; +} + +/* Macros used for manipulating bits in LEON3 GP Timer Control Register */ + +#define LEON3_IRQMPSTATUS_CPUNR 28 +#define LEON3_IRQMPSTATUS_BROADCAST 27 + + +#ifndef ASM + +/* + * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + * + * NOTE: For operations which are not atomic, this code disables interrupts + * to guarantee there are no intervening accesses to the same register. + * The operations which read the register, modify the value and then + * store the result back are vulnerable. + */ + +extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; + +#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ + rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) + +#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ + rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) + +#define LEON_Clear_interrupt( _source ) \ + do { \ + LEON3_IrqCtrl_Regs->iclear = (1 << (_source)); \ + } while (0) + +#define LEON_Force_interrupt( _source ) \ + do { \ + LEON3_IrqCtrl_Regs->iforce = (1 << (_source)); \ + } while (0) + +#define LEON_Is_interrupt_pending( _source ) \ + (LEON3_IrqCtrl_Regs->ipend & (1 << (_source))) + +#define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \ + (!(LEON3_IrqCtrl_Regs->mask[_cpu] & (1 << (_source)))) + +#define LEON_Cpu_Mask_interrupt( _source, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->mask[_cpu] &= ~(1 << (_source)); \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +#define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->mask[_cpu] |= (1 << (_source)); \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +#define LEON_Cpu_Disable_interrupt( _source, _previous, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + uint32_t _mask = 1 << (_source); \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + (_previous) = LEON3_IrqCtrl_Regs->mask[_cpu]; \ + LEON3_IrqCtrl_Regs->mask[_cpu] = _previous & ~_mask; \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + (_previous) &= _mask; \ + } while (0) + +#define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + uint32_t _mask = 1 << (_source); \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->mask[_cpu] = \ + (LEON3_IrqCtrl_Regs->mask[_cpu] & ~_mask) | (_previous); \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +/* Map single-cpu operations to local CPU */ +#define LEON_Is_interrupt_masked( _source ) \ + LEON_Cpu_Is_interrupt_masked(_source, _LEON3_Get_current_processor()) + +#define LEON_Mask_interrupt(_source) \ + LEON_Cpu_Mask_interrupt(_source, _LEON3_Get_current_processor()) + +#define LEON_Unmask_interrupt(_source) \ + LEON_Cpu_Unmask_interrupt(_source, _LEON3_Get_current_processor()) + +#define LEON_Disable_interrupt(_source, _previous) \ + LEON_Cpu_Disable_interrupt(_source, _previous, _LEON3_Get_current_processor()) + +#define LEON_Restore_interrupt(_source, _previous) \ + LEON_Cpu_Restore_interrupt(_source, _previous, _LEON3_Get_current_processor()) + +/* Make all SPARC BSPs have common macros for interrupt handling */ +#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) +#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) +#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) +#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) +#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) +#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) +#define BSP_Disable_interrupt(_source, _previous) \ + LEON_Disable_interrupt(_source, _prev) +#define BSP_Restore_interrupt(_source, _previous) \ + LEON_Restore_interrupt(_source, _previous) + +/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ +#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ + LEON_Cpu_Is_interrupt_masked(_source, _cpu) +#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ + LEON_Cpu_Unmask_interrupt(_source, _cpu) +#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ + LEON_Cpu_Mask_interrupt(_source, _cpu) +#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ + LEON_Cpu_Disable_interrupt(_source, _prev, _cpu) +#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ + LEON_Cpu_Restore_interrupt(_source, _previous, _cpu) + +/* + * Each timer control register is organized as follows: + * + * D0 - Enable + * 1 = enable counting + * 0 = hold scaler and counter + * + * D1 - Counter Reload + * 1 = reload counter at zero and restart + * 0 = stop counter at zero + * + * D2 - Counter Load + * 1 = load counter with preset value + * 0 = no function + * + */ + +#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 +#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 + +#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 + +#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 +#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 + +#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 +#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 + +#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 +#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 + +#if defined(RTEMS_MULTIPROCESSING) + #define LEON3_CLOCK_INDEX \ + (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) +#else + #define LEON3_CLOCK_INDEX 0 +#endif + +/* + * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to + * run with 1MHz. This is used to determine all clock frequencies of the PnP + * devices. See also ambapp_freq_init() and ambapp_freq_get(). + */ +#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 + +/* Load 32-bit word by forcing a cache-miss */ +static inline unsigned int leon_r32_no_cache(uintptr_t addr) +{ + unsigned int tmp; + __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); + return tmp; +} + +/* Let user override which on-chip APBUART will be debug UART + * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... + * 1 = APBUART[0] + * 2 = APBUART[1] + * 3 = APBUART[2] + * ... + */ +extern int syscon_uart_index; + +/* Let user override which on-chip APBUART will be debug UART + * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... + * 1 = APBUART[0] + * 2 = APBUART[1] + * 3 = APBUART[2] + * ... + */ +extern int debug_uart_index; + +void leon3_cpu_counter_initialize(void); + +/* GRLIB extended IRQ controller register */ +void leon3_ext_irq_init(void); + +void bsp_debug_uart_init(void); + +void leon3_power_down_loop(void) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + +static inline uint32_t leon3_get_cpu_count( + volatile struct irqmp_regs *irqmp +) +{ + uint32_t mpstat = irqmp->mpstat; + + return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; +} + +static inline void leon3_set_system_register(uint32_t addr, uint32_t val) +{ + __asm__ volatile( + "sta %1, [%0] 2" + : + : "r" (addr), "r" (val) + ); +} + +static inline uint32_t leon3_get_system_register(uint32_t addr) +{ + uint32_t val; + + __asm__ volatile( + "lda [%1] 2, %0" + : "=r" (val) + : "r" (addr) + ); + + return val; +} + +static inline void leon3_set_cache_control_register(uint32_t val) +{ + leon3_set_system_register(0x0, val); +} + +static inline uint32_t leon3_get_cache_control_register(void) +{ + return leon3_get_system_register(0x0); +} + +static inline bool leon3_data_cache_snooping_enabled(void) +{ + return leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS; +} + +static inline uint32_t leon3_get_inst_cache_config_register(void) +{ + return leon3_get_system_register(0x8); +} + +static inline uint32_t leon3_get_data_cache_config_register(void) +{ + return leon3_get_system_register(0xc); +} + +static inline bool leon3_irqmp_has_timestamp( + volatile struct irqmp_timestamp_regs *irqmp_ts +) +{ + return (irqmp_ts->control >> 27) > 0; +} + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* !_INCLUDE_LEON_h */ +/* end of include file */ + diff --git a/include/sparc/leon3/libcpu/byteorder.h b/include/sparc/leon3/libcpu/byteorder.h new file mode 100644 index 0000000000..9f67cf1c45 --- /dev/null +++ b/include/sparc/leon3/libcpu/byteorder.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/libcpu/byteorder.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/libcpu/byteorder.h> diff --git a/include/sparc/leon3/rtems/asm.h b/include/sparc/leon3/rtems/asm.h new file mode 100644 index 0000000000..5691a127d5 --- /dev/null +++ b/include/sparc/leon3/rtems/asm.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/asm.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/asm.h> diff --git a/include/sparc/leon3/rtems/score/cpu.h b/include/sparc/leon3/rtems/score/cpu.h new file mode 100644 index 0000000000..0c9d359cab --- /dev/null +++ b/include/sparc/leon3/rtems/score/cpu.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/cpu.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/cpu.h> diff --git a/include/sparc/leon3/rtems/score/cpuatomic.h b/include/sparc/leon3/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..6021d1c3f4 --- /dev/null +++ b/include/sparc/leon3/rtems/score/cpuatomic.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/rtems/score/cpuatomic.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/rtems/score/cpuatomic.h> diff --git a/include/sparc/leon3/rtems/score/types.h b/include/sparc/leon3/rtems/score/types.h new file mode 100644 index 0000000000..a6cb6998f4 --- /dev/null +++ b/include/sparc/leon3/rtems/score/types.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/types.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/types.h> diff --git a/include/sparc/leon3/tm27.h b/include/sparc/leon3/tm27.h new file mode 100644 index 0000000000..00921d4880 --- /dev/null +++ b/include/sparc/leon3/tm27.h @@ -0,0 +1,84 @@ +/** + * @file + * @ingroup sparc_leon3 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * COPYRIGHT (c) 2006. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Since the interrupt code for the SPARC supports both synchronous + * and asynchronous trap handlers, support for testing with both + * is included. + */ + +#define SIS_USE_SYNCHRONOUS_TRAP 0 + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +#if (SIS_USE_SYNCHRONOUS_TRAP == 1) + +#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); + +#define Cause_tm27_intr() \ + __asm__ volatile( "ta 0x10; nop " ); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/* + * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. + */ + +#else /* use a regular asynchronous trap */ + +#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 +#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) +#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 +#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); \ + set_vector( (handler), TEST_VECTOR2, 1 ); + +#define Cause_tm27_intr() \ + do { \ + LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ + nop(); \ + nop(); \ + nop(); \ + } while (0) + +#define Clear_tm27_intr() \ + LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) + +#define Lower_tm27_intr() /* empty */ + +#endif + +#endif diff --git a/include/sparc/ngmp/bsp.h b/include/sparc/ngmp/bsp.h new file mode 100644 index 0000000000..8962cad848 --- /dev/null +++ b/include/sparc/ngmp/bsp.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/leon3/bsp.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/leon3/bsp.h> diff --git a/include/sparc/ngmp/bsp/irq.h b/include/sparc/ngmp/bsp/irq.h new file mode 100644 index 0000000000..8abe802df0 --- /dev/null +++ b/include/sparc/ngmp/bsp/irq.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/leon3/bsp/irq.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/leon3/bsp/irq.h> diff --git a/include/sparc/ngmp/coverhd.h b/include/sparc/ngmp/coverhd.h new file mode 100644 index 0000000000..51037e4129 --- /dev/null +++ b/include/sparc/ngmp/coverhd.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/coverhd.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/coverhd.h> diff --git a/include/sparc/ngmp/leon.h b/include/sparc/ngmp/leon.h new file mode 100644 index 0000000000..1f3e95aa86 --- /dev/null +++ b/include/sparc/ngmp/leon.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/leon3/leon.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/leon3/leon.h> diff --git a/include/sparc/ngmp/libcpu/byteorder.h b/include/sparc/ngmp/libcpu/byteorder.h new file mode 100644 index 0000000000..9f67cf1c45 --- /dev/null +++ b/include/sparc/ngmp/libcpu/byteorder.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/libcpu/byteorder.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/libcpu/byteorder.h> diff --git a/include/sparc/ngmp/rtems/asm.h b/include/sparc/ngmp/rtems/asm.h new file mode 100644 index 0000000000..5691a127d5 --- /dev/null +++ b/include/sparc/ngmp/rtems/asm.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/asm.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/asm.h> diff --git a/include/sparc/ngmp/rtems/score/cpu.h b/include/sparc/ngmp/rtems/score/cpu.h new file mode 100644 index 0000000000..0c9d359cab --- /dev/null +++ b/include/sparc/ngmp/rtems/score/cpu.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/cpu.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/cpu.h> diff --git a/include/sparc/ngmp/rtems/score/cpuatomic.h b/include/sparc/ngmp/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..6021d1c3f4 --- /dev/null +++ b/include/sparc/ngmp/rtems/score/cpuatomic.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/rtems/score/cpuatomic.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/rtems/score/cpuatomic.h> diff --git a/include/sparc/ngmp/rtems/score/types.h b/include/sparc/ngmp/rtems/score/types.h new file mode 100644 index 0000000000..a6cb6998f4 --- /dev/null +++ b/include/sparc/ngmp/rtems/score/types.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/types.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/types.h> diff --git a/include/sparc/ngmp/tm27.h b/include/sparc/ngmp/tm27.h new file mode 100644 index 0000000000..bdee644bea --- /dev/null +++ b/include/sparc/ngmp/tm27.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/leon3/tm27.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/leon3/tm27.h> diff --git a/include/sparc/sis/bsp.h b/include/sparc/sis/bsp.h new file mode 100644 index 0000000000..c46116e5e3 --- /dev/null +++ b/include/sparc/sis/bsp.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/bsp.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/bsp.h> diff --git a/include/sparc/sis/bsp/irq.h b/include/sparc/sis/bsp/irq.h new file mode 100644 index 0000000000..216148b882 --- /dev/null +++ b/include/sparc/sis/bsp/irq.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/bsp/irq.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/bsp/irq.h> diff --git a/include/sparc/sis/coverhd.h b/include/sparc/sis/coverhd.h new file mode 100644 index 0000000000..51037e4129 --- /dev/null +++ b/include/sparc/sis/coverhd.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/coverhd.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/coverhd.h> diff --git a/include/sparc/sis/libcpu/byteorder.h b/include/sparc/sis/libcpu/byteorder.h new file mode 100644 index 0000000000..9f67cf1c45 --- /dev/null +++ b/include/sparc/sis/libcpu/byteorder.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/libcpu/byteorder.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/libcpu/byteorder.h> diff --git a/include/sparc/sis/rtems/asm.h b/include/sparc/sis/rtems/asm.h new file mode 100644 index 0000000000..5691a127d5 --- /dev/null +++ b/include/sparc/sis/rtems/asm.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/asm.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/asm.h> diff --git a/include/sparc/sis/rtems/score/cpu.h b/include/sparc/sis/rtems/score/cpu.h new file mode 100644 index 0000000000..0c9d359cab --- /dev/null +++ b/include/sparc/sis/rtems/score/cpu.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/cpu.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/cpu.h> diff --git a/include/sparc/sis/rtems/score/cpuatomic.h b/include/sparc/sis/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..6021d1c3f4 --- /dev/null +++ b/include/sparc/sis/rtems/score/cpuatomic.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/rtems/score/cpuatomic.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <arm/altcycv_devkit/rtems/score/cpuatomic.h> diff --git a/include/sparc/sis/rtems/score/types.h b/include/sparc/sis/rtems/score/types.h new file mode 100644 index 0000000000..a6cb6998f4 --- /dev/null +++ b/include/sparc/sis/rtems/score/types.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/rtems/score/types.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/rtems/score/types.h> diff --git a/include/sparc/sis/tm27.h b/include/sparc/sis/tm27.h new file mode 100644 index 0000000000..92196c7a9a --- /dev/null +++ b/include/sparc/sis/tm27.h @@ -0,0 +1,5 @@ +#if defined(HEADER_WARNING_DUPLICATE) /* sparc/erc32/tm27.h */ +#warning "This header should not be included directly. (duplicate)" +#endif + +#include <sparc/erc32/tm27.h> |