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-rw-r--r--include/powerpc/pghplus/bsp.h171
-rw-r--r--include/powerpc/pghplus/bsp/8xx_immap.h477
-rw-r--r--include/powerpc/pghplus/bsp/irq.h160
-rw-r--r--include/powerpc/pghplus/coverhd.h120
-rw-r--r--include/powerpc/pghplus/libcpu/byteorder.h5
-rw-r--r--include/powerpc/pghplus/libcpu/mmu.h5
-rw-r--r--include/powerpc/pghplus/rtems/asm.h5
-rw-r--r--include/powerpc/pghplus/rtems/score/cpu.h5
-rw-r--r--include/powerpc/pghplus/rtems/score/cpuatomic.h5
-rw-r--r--include/powerpc/pghplus/rtems/score/types.h5
-rw-r--r--include/powerpc/pghplus/tm27.h5
11 files changed, 963 insertions, 0 deletions
diff --git a/include/powerpc/pghplus/bsp.h b/include/powerpc/pghplus/bsp.h
new file mode 100644
index 0000000000..fa404e4f5d
--- /dev/null
+++ b/include/powerpc/pghplus/bsp.h
@@ -0,0 +1,171 @@
+/*
+ * RTEMS TQM8xx BSP
+ * This include file contains all board IO definitions.
+ */
+
+/*
+ * This file has been adapted to MPC8xx by:
+ * Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * COPYRIGHT (c) 1989-2008.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _BSP_H
+#define _BSP_H
+
+/*
+ * indicate, that BSP is booted via TQMMon
+ */
+#define BSP_HAS_TQMMON
+
+#include <libcpu/powerpc-utility.h>
+
+LINKER_SYMBOL(TopRamReserved);
+
+LINKER_SYMBOL( bsp_ram_start);
+LINKER_SYMBOL( bsp_ram_end);
+LINKER_SYMBOL( bsp_ram_size);
+
+LINKER_SYMBOL( bsp_rom_start);
+LINKER_SYMBOL( bsp_rom_end);
+LINKER_SYMBOL( bsp_rom_size);
+
+LINKER_SYMBOL( bsp_section_text_start);
+LINKER_SYMBOL( bsp_section_text_end);
+LINKER_SYMBOL( bsp_section_text_size);
+
+LINKER_SYMBOL( bsp_section_data_start);
+LINKER_SYMBOL( bsp_section_data_end);
+LINKER_SYMBOL( bsp_section_data_size);
+
+LINKER_SYMBOL( bsp_section_bss_start);
+LINKER_SYMBOL( bsp_section_bss_end);
+LINKER_SYMBOL( bsp_section_bss_size);
+
+LINKER_SYMBOL( bsp_interrupt_stack_start);
+LINKER_SYMBOL( bsp_interrupt_stack_end);
+LINKER_SYMBOL( bsp_interrupt_stack_size);
+
+LINKER_SYMBOL( bsp_work_area_start);
+
+#ifndef ASM
+
+#include <bspopts.h>
+
+#include <rtems.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+#include <rtems/irq.h>
+#include <mpc8xx.h>
+#include <mpc8xx/cpm.h>
+#include <mpc8xx/mmu.h>
+#include <mpc8xx/console.h>
+#include <bsp/vectors.h>
+#include <bsp/tqm.h>
+#include <libcpu/powerpc-utility.h>
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Network driver configuration
+ */
+struct rtems_bsdnet_ifconfig;
+
+#if BSP_USE_NETWORK_FEC
+extern int rtems_fec_enet_driver_attach (struct rtems_bsdnet_ifconfig *config,
+ int attaching);
+#define RTEMS_BSP_FEC_NETWORK_DRIVER_NAME "fec1"
+#define RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH rtems_fec_enet_driver_attach
+#endif
+
+#if BSP_USE_NETWORK_SCC
+extern int rtems_scc_enet_driver_attach (struct rtems_bsdnet_ifconfig *config,
+ int attaching);
+#define RTEMS_BSP_SCC_NETWORK_DRIVER_NAME "scc1"
+#define RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH rtems_scc_enet_driver_attach
+#endif
+
+#if BSP_USE_NETWORK_FEC
+#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_FEC_NETWORK_DRIVER_NAME
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH
+#elif BSP_USE_NETWORK_SCC
+#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_SCC_NETWORK_DRIVER_NAME
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH
+#endif
+/*
+ * We need to decide how much memory will be non-cacheable. This
+ * will mainly be memory that will be used in DMA (network and serial
+ * buffers).
+ */
+#define NOCACHE_MEM_SIZE 512*1024
+
+/*
+ * indicate, that BSP has IDE driver
+ */
+#undef RTEMS_BSP_HAS_IDE_DRIVER
+
+/*
+ * SPI driver configuration
+ */
+
+ /* select values for SPI addressing */
+#define PGHPLUS_SPI_ADDR_EEPROM 0
+#define PGHPLUS_SPI_ADDR_DISP4 1
+ /* NOTE: DISP4 occupies two consecutive addresses for data and control port */
+#define PGHPLUS_SPI_ADDR_DISP4_DATA (PGHPLUS_SPI_ADDR_DISP4)
+#define PGHPLUS_SPI_ADDR_DISP4_CTRL (PGHPLUS_SPI_ADDR_DISP4_DATA+1)
+
+ /* bit masks for Port B lines */
+#define PGHPLUS_PB_SPI_EEP_CE_MSK (1<< 0)
+#define PGHPLUS_PB_SPI_DISP4_RS_MSK (1<<15)
+#define PGHPLUS_PB_SPI_DISP4_CE_MSK (1<<14)
+
+/*
+ * our (internal) bus frequency
+ */
+extern uint32_t BSP_bus_frequency;
+
+/*
+ * Interfaces to required Clock Driver support methods
+ */
+int BSP_disconnect_clock_handler(void);
+int BSP_connect_clock_handler (rtems_irq_hdl);
+
+extern uint32_t bsp_clock_speed;
+
+char serial_getc(void);
+
+int serial_tstc(void);
+
+void serial_init(void);
+
+int mbx8xx_console_get_configuration(void);
+
+void _InitTQM8xx (void);
+
+rtems_status_code bsp_register_spi(void);
+
+void *bsp_idle_thread( uintptr_t ignored );
+
+void cpu_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif
diff --git a/include/powerpc/pghplus/bsp/8xx_immap.h b/include/powerpc/pghplus/bsp/8xx_immap.h
new file mode 100644
index 0000000000..c1c414e25f
--- /dev/null
+++ b/include/powerpc/pghplus/bsp/8xx_immap.h
@@ -0,0 +1,477 @@
+/*===============================================================*\
+| Project: RTEMS BSP support for TQ modules |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below. |
+| Adaptions, modifications, enhancements and any recent parts of |
+| the code are: |
+| Copyright (c) 2007 |
+| Embedded Brains GmbH |
+| Obere Lagerstr. 30 |
+| D-82178 Puchheim |
+| Germany |
+| rtems@embedded-brains.de |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be |
+| found in the file LICENSE in this distribution or at |
+| |
+| http://www.rtems.org/license/LICENSE. |
+| |
++-----------------------------------------------------------------+
+| this file contains definitions to interact with TQC's |
+| processor modules |
+\*===============================================================*/
+/* derived from mbx8xx BSP */
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions. It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try. -- Dan
+ */
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef struct sys_conf {
+ unsigned int sc_siumcr;
+ unsigned int sc_sypcr;
+ unsigned int sc_swt;
+ char res1[2];
+ unsigned short sc_swsr;
+ unsigned int sc_sipend;
+ unsigned int sc_simask;
+ unsigned int sc_siel;
+ unsigned int sc_sivec;
+ unsigned int sc_tesr;
+ char res2[0xc];
+ unsigned int sc_sdcr;
+ char res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+ unsigned int pcmc_pbr0;
+ unsigned int pcmc_por0;
+ unsigned int pcmc_pbr1;
+ unsigned int pcmc_por1;
+ unsigned int pcmc_pbr2;
+ unsigned int pcmc_por2;
+ unsigned int pcmc_pbr3;
+ unsigned int pcmc_por3;
+ unsigned int pcmc_pbr4;
+ unsigned int pcmc_por4;
+ unsigned int pcmc_pbr5;
+ unsigned int pcmc_por5;
+ unsigned int pcmc_pbr6;
+ unsigned int pcmc_por6;
+ unsigned int pcmc_pbr7;
+ unsigned int pcmc_por7;
+ char res1[0x20];
+ unsigned int pcmc_pgcra;
+ unsigned int pcmc_pgcrb;
+ unsigned int pcmc_pscr;
+ char res2[4];
+ unsigned int pcmc_pipr;
+ char res3[4];
+ unsigned int pcmc_per;
+ char res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct mem_ctlr {
+ unsigned int memc_br0;
+ unsigned int memc_or0;
+ unsigned int memc_br1;
+ unsigned int memc_or1;
+ unsigned int memc_br2;
+ unsigned int memc_or2;
+ unsigned int memc_br3;
+ unsigned int memc_or3;
+ unsigned int memc_br4;
+ unsigned int memc_or4;
+ unsigned int memc_br5;
+ unsigned int memc_or5;
+ unsigned int memc_br6;
+ unsigned int memc_or6;
+ unsigned int memc_br7;
+ unsigned int memc_or7;
+ char res1[0x24];
+ unsigned int memc_mar;
+ unsigned int memc_mcr;
+ char res2[4];
+ unsigned int memc_mamr;
+ unsigned int memc_mbmr;
+ unsigned short memc_mstat;
+ unsigned short memc_mptpr;
+ unsigned int memc_mdr;
+ char res3[0x80];
+} memctl8xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct sys_int_timers {
+ unsigned short sit_tbscr;
+ unsigned int sit_tbreff0;
+ unsigned int sit_tbreff1;
+ char res1[0x14];
+ unsigned short sit_rtcsc;
+ unsigned int sit_rtc;
+ unsigned int sit_rtsec;
+ unsigned int sit_rtcal;
+ char res2[0x10];
+ unsigned short sit_piscr;
+ char res3[2];
+ unsigned int sit_pitc;
+ unsigned int sit_pitr;
+ char res4[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00)
+#define TBSCR_REFA ((unsigned short)0x0080)
+#define TBSCR_REFB ((unsigned short)0x0040)
+#define TBSCR_REFAE ((unsigned short)0x0008)
+#define TBSCR_REFBE ((unsigned short)0x0004)
+#define TBSCR_TBF ((unsigned short)0x0002)
+#define TBSCR_TBE ((unsigned short)0x0001)
+
+#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00)
+#define RTCSC_SEC ((unsigned short)0x0080)
+#define RTCSC_ALR ((unsigned short)0x0040)
+#define RTCSC_38K ((unsigned short)0x0010)
+#define RTCSC_SIE ((unsigned short)0x0008)
+#define RTCSC_ALE ((unsigned short)0x0004)
+#define RTCSC_RTF ((unsigned short)0x0002)
+#define RTCSC_RTE ((unsigned short)0x0001)
+
+#define PISCR_PIRQ_MASK ((unsigned short)0xff00)
+#define PISCR_PS ((unsigned short)0x0080)
+#define PISCR_PIE ((unsigned short)0x0004)
+#define PISCR_PTF ((unsigned short)0x0002)
+#define PISCR_PTE ((unsigned short)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+ unsigned int car_sccr;
+ unsigned int car_plprcr;
+ unsigned int car_rsr;
+ char res[0x74]; /* Reserved area */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+ unsigned int sitk_tbscrk;
+ unsigned int sitk_tbreff0k;
+ unsigned int sitk_tbreff1k;
+ unsigned int sitk_tbk;
+ char res1[0x10];
+ unsigned int sitk_rtcsck;
+ unsigned int sitk_rtck;
+ unsigned int sitk_rtseck;
+ unsigned int sitk_rtcalk;
+ char res2[0x10];
+ unsigned int sitk_piscrk;
+ unsigned int sitk_pitck;
+ char res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+ unsigned int cark_sccrk;
+ unsigned int cark_plprcrk;
+ unsigned int cark_rsrk;
+ char res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY ((unsigned int)0x55ccaa33)
+
+/* LCD interface. MPC821 Only.
+*/
+typedef struct lcd {
+ unsigned short lcd_lcolr[16];
+ char res[0x20];
+ unsigned int lcd_lccr;
+ unsigned int lcd_lchcr;
+ unsigned int lcd_lcvcr;
+ char res2[4];
+ unsigned int lcd_lcfaa;
+ unsigned int lcd_lcfba;
+ char lcd_lcsr;
+ char res3[0x7];
+} lcd8xx_t;
+
+/* I2C
+*/
+typedef struct i2c {
+ unsigned char i2c_i2mod;
+ char res1[3];
+ unsigned char i2c_i2add;
+ char res2[3];
+ unsigned char i2c_i2brg;
+ char res3[3];
+ unsigned char i2c_i2com;
+ char res4[3];
+ unsigned char i2c_i2cer;
+ char res5[3];
+ unsigned char i2c_i2cmr;
+ char res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+ char res1[4];
+ unsigned int sdma_sdar;
+ unsigned char sdma_sdsr;
+ char res3[3];
+ unsigned char sdma_sdmr;
+ char res4[3];
+ unsigned char sdma_idsr1;
+ char res5[3];
+ unsigned char sdma_idmr1;
+ char res6[3];
+ unsigned char sdma_idsr2;
+ char res7[3];
+ unsigned char sdma_idmr2;
+ char res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+ unsigned short cpic_civr;
+ char res[0xe];
+ unsigned int cpic_cicr;
+ unsigned int cpic_cipr;
+ unsigned int cpic_cimr;
+ unsigned int cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+ unsigned short iop_padir;
+ unsigned short iop_papar;
+ unsigned short iop_paodr;
+ unsigned short iop_padat;
+ char res1[8];
+ unsigned short iop_pcdir;
+ unsigned short iop_pcpar;
+ unsigned short iop_pcso;
+ unsigned short iop_pcdat;
+ unsigned short iop_pcint;
+ char res2[6];
+ unsigned short iop_pddir;
+ unsigned short iop_pdpar;
+ char res3[2];
+ unsigned short iop_pddat;
+ char res4[8];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+ unsigned short cpmt_tgcr;
+ char res1[0xe];
+ unsigned short cpmt_tmr1;
+ unsigned short cpmt_tmr2;
+ unsigned short cpmt_trr1;
+ unsigned short cpmt_trr2;
+ unsigned short cpmt_tcr1;
+ unsigned short cpmt_tcr2;
+ unsigned short cpmt_tcn1;
+ unsigned short cpmt_tcn2;
+ unsigned short cpmt_tmr3;
+ unsigned short cpmt_tmr4;
+ unsigned short cpmt_trr3;
+ unsigned short cpmt_trr4;
+ unsigned short cpmt_tcr3;
+ unsigned short cpmt_tcr4;
+ unsigned short cpmt_tcn3;
+ unsigned short cpmt_tcn4;
+ unsigned short cpmt_ter1;
+ unsigned short cpmt_ter2;
+ unsigned short cpmt_ter3;
+ unsigned short cpmt_ter4;
+ char res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc { /* Serial communication channels */
+ unsigned int scc_gsmrl;
+ unsigned int scc_gsmrh;
+ unsigned short scc_pmsr;
+ char res1[2];
+ unsigned short scc_todr;
+ unsigned short scc_dsr;
+ unsigned short scc_scce;
+ char res2[2];
+ unsigned short scc_sccm;
+ char res3;
+ unsigned char scc_sccs;
+ char res4[8];
+} scc_t;
+
+typedef struct smc { /* Serial management channels */
+ char res1[2];
+ unsigned short smc_smcmr;
+ char res2[2];
+ unsigned char smc_smce;
+ char res3[3];
+ unsigned char smc_smcm;
+ char res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+typedef struct fec {
+ unsigned int fec_addr_low; /* LS 32 bits of station address */
+ unsigned short fec_addr_high; /* MS 16 bits of address */
+ unsigned short res1;
+ unsigned int fec_hash_table_high;
+ unsigned int fec_hash_table_low;
+ unsigned int fec_r_des_start;
+ unsigned int fec_x_des_start;
+ unsigned int fec_r_buff_size;
+ unsigned int res2[9];
+ unsigned int fec_ecntrl;
+ unsigned int fec_ievent;
+ unsigned int fec_imask;
+ unsigned int fec_ivec;
+ unsigned int fec_r_des_active;
+ unsigned int fec_x_des_active;
+ unsigned int res3[10];
+ unsigned int fec_mii_data;
+ unsigned int fec_mii_speed;
+ unsigned int res4[17];
+ unsigned int fec_r_bound;
+ unsigned int fec_r_fstart;
+ unsigned int res5[6];
+ unsigned int fec_x_fstart;
+ unsigned int res6[17];
+ unsigned int fec_fun_code;
+ unsigned int res7[3];
+ unsigned int fec_r_cntrl;
+ unsigned int fec_r_hash;
+ unsigned int res8[14];
+ unsigned int fec_x_cntrl;
+ unsigned int res9[0x1e];
+} fec_t;
+
+typedef struct comm_proc {
+ /* General control and status registers.
+ */
+ unsigned short cp_cpcr;
+ char res1[2];
+ unsigned short cp_rccr;
+ char res2[6];
+ unsigned short cp_cpmcr1;
+ unsigned short cp_cpmcr2;
+ unsigned short cp_cpmcr3;
+ unsigned short cp_cpmcr4;
+ char res3[2];
+ unsigned short cp_rter;
+ char res4[2];
+ unsigned short cp_rtmr;
+ char res5[0x14];
+
+ /* Baud rate generators.
+ */
+ unsigned int cp_brgc1;
+ unsigned int cp_brgc2;
+ unsigned int cp_brgc3;
+ unsigned int cp_brgc4;
+
+ /* Serial Communication Channels.
+ */
+ scc_t cp_scc[4];
+
+ /* Serial Management Channels.
+ */
+ smc_t cp_smc[2];
+
+ /* Serial Peripheral Interface.
+ */
+ unsigned short cp_spmode;
+ char res6[4];
+ unsigned char cp_spie;
+ char res7[3];
+ unsigned char cp_spim;
+ char res8[2];
+ unsigned char cp_spcom;
+ char res9[2];
+
+ /* Parallel Interface Port.
+ */
+ char res10[2];
+ unsigned short cp_pipc;
+ char res11[2];
+ unsigned short cp_ptpr;
+ unsigned int cp_pbdir;
+ unsigned int cp_pbpar;
+ char res12[2];
+ unsigned short cp_pbodr;
+ unsigned int cp_pbdat;
+ char res13[0x18];
+
+ /* Serial Interface and Time Slot Assignment.
+ */
+ unsigned int cp_simode;
+ unsigned char cp_sigmr;
+ char res14;
+ unsigned char cp_sistr;
+ unsigned char cp_sicmr;
+ char res15[4];
+ unsigned int cp_sicr;
+ unsigned int cp_sirp;
+ char res16[0x10c];
+ unsigned char cp_siram[0x200];
+
+ /* The fast ethernet controller is not really part of the CPM,
+ * but it resides in the address space.
+ */
+ fec_t cp_fec;
+ char res18[0x1000];
+
+ /* Dual Ported RAM follows.
+ * There are many different formats for this memory area
+ * depending upon the devices used and options chosen.
+ */
+ unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */
+ unsigned char res19[0xc00];
+ unsigned char cp_dparam[0x400]; /* Parameter RAM */
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+ sysconf8xx_t im_siu_conf; /* SIU Configuration */
+ pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
+ memctl8xx_t im_memctl; /* Memory Controller */
+ sit8xx_t im_sit; /* System integration timers */
+ car8xx_t im_clkrst; /* Clocks and reset */
+ sitk8xx_t im_sitk; /* Sys int timer keys */
+ cark8xx_t im_clkrstk; /* Clocks and reset keys */
+ lcd8xx_t im_lcd; /* LCD (821 only) */
+ i2c8xx_t im_i2c; /* I2C control/status */
+ sdma8xx_t im_sdma; /* SDMA control/status */
+ cpic8xx_t im_cpic; /* CPM Interrupt Controller */
+ iop8xx_t im_ioport; /* IO Port control/status */
+ cpmtimer8xx_t im_cpmtimer; /* CPM timers */
+ cpm8xx_t im_cpm; /* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
diff --git a/include/powerpc/pghplus/bsp/irq.h b/include/powerpc/pghplus/bsp/irq.h
new file mode 100644
index 0000000000..2d66829037
--- /dev/null
+++ b/include/powerpc/pghplus/bsp/irq.h
@@ -0,0 +1,160 @@
+/*===============================================================*\
+| Project: RTEMS TQM8xx BSP |
++-----------------------------------------------------------------+
+| This file has been adapted to MPC8xx by |
+| Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> |
+| Copyright (c) 2008 |
+| Embedded Brains GmbH |
+| Obere Lagerstr. 30 |
+| D-82178 Puchheim |
+| Germany |
+| rtems@embedded-brains.de |
+| |
+| See the other copyright notice below for the original parts. |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be |
+| found in the file LICENSE in this distribution or at |
+| |
+| http://www.rtems.org/license/LICENSE. |
+| |
++-----------------------------------------------------------------+
+| this file contains the console driver |
+\*===============================================================*/
+/* derived from: generic MPC83xx BSP */
+#ifndef TQM8xx_IRQ_IRQ_H
+#define TQM8xx_IRQ_IRQ_H
+
+#include <stdbool.h>
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/*
+ * the following definitions specify the indices used
+ * to interface the interrupt handler API
+ */
+
+/*
+ * Peripheral IRQ handlers related definitions
+ */
+#define BSP_SIU_PER_IRQ_NUMBER 16
+#define BSP_SIU_IRQ_LOWEST_OFFSET 0
+#define BSP_SIU_IRQ_MAX_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET\
+ +BSP_SIU_PER_IRQ_NUMBER-1)
+
+#define BSP_IS_SIU_IRQ(irqnum) \
+ (((irqnum) >= BSP_SIU_IRQ_LOWEST_OFFSET) && \
+ ((irqnum) <= BSP_SIU_IRQ_MAX_OFFSET))
+
+#define BSP_CPM_PER_IRQ_NUMBER 32
+#define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_MAX_OFFSET+1)
+#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET\
+ +BSP_CPM_PER_IRQ_NUMBER-1)
+
+#define BSP_IS_CPM_IRQ(irqnum) \
+ (((irqnum) >= BSP_CPM_IRQ_LOWEST_OFFSET) && \
+ ((irqnum) <= BSP_CPM_IRQ_MAX_OFFSET))
+/*
+ * Processor IRQ handlers related definitions
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER 1
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET+1)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
+ +BSP_PROCESSOR_IRQ_NUMBER-1)
+
+#define BSP_IS_PROCESSOR_IRQ(irqnum) \
+ (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \
+ ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
+/*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
+#define BSP_LOWEST_OFFSET BSP_SIU_IRQ_LOWEST_OFFSET
+#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET
+
+#define BSP_IS_VALID_IRQ(irqnum) \
+ (BSP_IS_PROCESSOR_IRQ(irqnum) \
+ || BSP_IS_SIU_IRQ(irqnum) \
+ || BSP_IS_CPM_IRQ(irqnum))
+
+#ifndef ASM
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * index table for the module specific handlers, a few entries are only placeholders
+ */
+ typedef enum {
+ BSP_SIU_EXT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 0,
+ BSP_SIU_INT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 1,
+ BSP_SIU_EXT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 2,
+ BSP_SIU_INT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 3,
+ BSP_SIU_EXT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 4,
+ BSP_SIU_INT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 5,
+ BSP_SIU_EXT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 6,
+ BSP_SIU_INT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 7,
+ BSP_SIU_EXT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 8,
+ BSP_SIU_INT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 9,
+ BSP_SIU_EXT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 10,
+ BSP_SIU_INT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 11,
+ BSP_SIU_EXT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 12,
+ BSP_SIU_INT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 13,
+ BSP_SIU_EXT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 14,
+ BSP_SIU_INT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 15,
+ BSP_SIU_IRQ_LAST = BSP_SIU_IRQ_MAX_OFFSET,
+ /*
+ * Some CPM IRQ symbolic name definition
+ */
+ BSP_CPM_IRQ_ERROR = (BSP_CPM_IRQ_LOWEST_OFFSET),
+ BSP_CPM_IRQ_PARALLEL_IO_PC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 1),
+ BSP_CPM_IRQ_PARALLEL_IO_PC5 = (BSP_CPM_IRQ_LOWEST_OFFSET + 2),
+ BSP_CPM_IRQ_SMC2_OR_PIP = (BSP_CPM_IRQ_LOWEST_OFFSET + 3),
+ BSP_CPM_IRQ_SMC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 4),
+ BSP_CPM_IRQ_SPI = (BSP_CPM_IRQ_LOWEST_OFFSET + 5),
+ BSP_CPM_IRQ_PARALLEL_IO_PC6 = (BSP_CPM_IRQ_LOWEST_OFFSET + 6),
+ BSP_CPM_IRQ_TIMER_4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 7),
+ BSP_CPM_IRQ_PARALLEL_IO_PC7 = (BSP_CPM_IRQ_LOWEST_OFFSET + 9),
+ BSP_CPM_IRQ_PARALLEL_IO_PC8 = (BSP_CPM_IRQ_LOWEST_OFFSET + 10),
+ BSP_CPM_IRQ_PARALLEL_IO_PC9 = (BSP_CPM_IRQ_LOWEST_OFFSET + 11),
+ BSP_CPM_IRQ_TIMER_3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 12),
+ BSP_CPM_IRQ_PARALLEL_IO_PC10= (BSP_CPM_IRQ_LOWEST_OFFSET + 14),
+ BSP_CPM_IRQ_PARALLEL_IO_PC11= (BSP_CPM_IRQ_LOWEST_OFFSET + 15),
+ BSP_CPM_I2C = (BSP_CPM_IRQ_LOWEST_OFFSET + 16),
+ BSP_CPM_RISC_TIMER_TABLE = (BSP_CPM_IRQ_LOWEST_OFFSET + 17),
+ BSP_CPM_IRQ_TIMER_2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 18),
+ BSP_CPM_IDMA2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 20),
+ BSP_CPM_IDMA1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 21),
+ BSP_CPM_SDMA_CHANNEL_BUS_ERR= (BSP_CPM_IRQ_LOWEST_OFFSET + 22),
+ BSP_CPM_IRQ_PARALLEL_IO_PC12= (BSP_CPM_IRQ_LOWEST_OFFSET + 23),
+ BSP_CPM_IRQ_PARALLEL_IO_PC13= (BSP_CPM_IRQ_LOWEST_OFFSET + 24),
+ BSP_CPM_IRQ_TIMER_1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 25),
+ BSP_CPM_IRQ_PARALLEL_IO_PC14= (BSP_CPM_IRQ_LOWEST_OFFSET + 26),
+ BSP_CPM_IRQ_SCC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 27),
+ BSP_CPM_IRQ_SCC3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 28),
+ BSP_CPM_IRQ_SCC2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 29),
+ BSP_CPM_IRQ_SCC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 30),
+ BSP_CPM_IRQ_PARALLEL_IO_PC15= (BSP_CPM_IRQ_LOWEST_OFFSET + 31),
+ BSP_CPM_IRQ_LAST = BSP_CPM_IRQ_MAX_OFFSET,
+ } rtems_irq_symbolic_name;
+
+ /*
+ * Symbolic name for CPM interrupt on SIU Internal level 2
+ */
+#define BSP_CPM_INTERRUPT BSP_SIU_INT_IRQ_2
+#define BSP_PERIODIC_TIMER BSP_SIU_INT_IRQ_6
+#define BSP_FAST_ETHERNET_CTRL BSP_SIU_INT_IRQ_3
+
+#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
+
+#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
+
+extern int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ASM */
+
+#endif /* TQM8XX_IRQ_IRQ_H */
diff --git a/include/powerpc/pghplus/coverhd.h b/include/powerpc/pghplus/coverhd.h
new file mode 100644
index 0000000000..9bd1c357c8
--- /dev/null
+++ b/include/powerpc/pghplus/coverhd.h
@@ -0,0 +1,120 @@
+/**
+ * @file
+ * @ingroup powerpc_tqm8xx
+ * @brief C Overhead definitions
+ */
+
+/*
+ *
+ * This include file has defines to represent the overhead associated
+ * with calling a particular directive from C. These are used in the
+ * Timing Test Suite to ignore the overhead required to pass arguments
+ * to directives. On some CPUs and/or target boards, this overhead
+ * is significant and makes it difficult to distinguish internal
+ * RTEMS execution time from that used to call the directive.
+ * This file should be updated after running the C overhead timing
+ * test. Once this update has been performed, the RTEMS Time Test
+ * Suite should be rebuilt to account for these overhead times in the
+ * timing results.
+ *
+ * NOTE: If these are all zero, then the times reported include
+ * all calling overhead including passing of arguments.
+ *
+ * COPYRIGHT (c) 1989-1998.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * 133 MHz processor, cache enabled.
+ */
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0
+#define CALLING_OVERHEAD_TASK_CREATE 1
+#define CALLING_OVERHEAD_TASK_IDENT 0
+#define CALLING_OVERHEAD_TASK_START 0
+#define CALLING_OVERHEAD_TASK_RESTART 0
+#define CALLING_OVERHEAD_TASK_DELETE 0
+#define CALLING_OVERHEAD_TASK_SUSPEND 0
+#define CALLING_OVERHEAD_TASK_RESUME 0
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0
+#define CALLING_OVERHEAD_TASK_MODE 0
+#define CALLING_OVERHEAD_TASK_GET_NOTE 0
+#define CALLING_OVERHEAD_TASK_SET_NOTE 0
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0
+#define CALLING_OVERHEAD_INTERRUPT_CATCH 0
+#define CALLING_OVERHEAD_CLOCK_GET 1
+#define CALLING_OVERHEAD_CLOCK_SET 1
+#define CALLING_OVERHEAD_CLOCK_TICK 0
+
+#define CALLING_OVERHEAD_TIMER_CREATE 0
+#define CALLING_OVERHEAD_TIMER_IDENT 0
+#define CALLING_OVERHEAD_TIMER_DELETE 0
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1
+#define CALLING_OVERHEAD_TIMER_RESET 0
+#define CALLING_OVERHEAD_TIMER_CANCEL 0
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0
+
+#define CALLING_OVERHEAD_EVENT_SEND 0
+#define CALLING_OVERHEAD_EVENT_RECEIVE 0
+#define CALLING_OVERHEAD_SIGNAL_CATCH 0
+#define CALLING_OVERHEAD_SIGNAL_SEND 0
+#define CALLING_OVERHEAD_PARTITION_CREATE 1
+#define CALLING_OVERHEAD_PARTITION_IDENT 0
+#define CALLING_OVERHEAD_PARTITION_DELETE 0
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0
+#define CALLING_OVERHEAD_REGION_CREATE 1
+#define CALLING_OVERHEAD_REGION_IDENT 0
+#define CALLING_OVERHEAD_REGION_DELETE 0
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0
+#define CALLING_OVERHEAD_PORT_CREATE 0
+#define CALLING_OVERHEAD_PORT_IDENT 0
+#define CALLING_OVERHEAD_PORT_DELETE 0
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
+
+#define CALLING_OVERHEAD_IO_INITIALIZE 0
+#define CALLING_OVERHEAD_IO_OPEN 0
+#define CALLING_OVERHEAD_IO_CLOSE 0
+#define CALLING_OVERHEAD_IO_READ 0
+#define CALLING_OVERHEAD_IO_WRITE 0
+#define CALLING_OVERHEAD_IO_CONTROL 0
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/powerpc/pghplus/libcpu/byteorder.h b/include/powerpc/pghplus/libcpu/byteorder.h
new file mode 100644
index 0000000000..9fd018eda4
--- /dev/null
+++ b/include/powerpc/pghplus/libcpu/byteorder.h
@@ -0,0 +1,5 @@
+#if defined(HEADER_WARNING_DUPLICATE) /* powerpc/beatnik/libcpu/byteorder.h */
+#warning "This header should not be included directly. (duplicate)"
+#endif
+
+#include <powerpc/beatnik/libcpu/byteorder.h>
diff --git a/include/powerpc/pghplus/libcpu/mmu.h b/include/powerpc/pghplus/libcpu/mmu.h
new file mode 100644
index 0000000000..7d335e8940
--- /dev/null
+++ b/include/powerpc/pghplus/libcpu/mmu.h
@@ -0,0 +1,5 @@
+#if defined(HEADER_WARNING_DUPLICATE) /* powerpc/beatnik/libcpu/mmu.h */
+#warning "This header should not be included directly. (duplicate)"
+#endif
+
+#include <powerpc/beatnik/libcpu/mmu.h>
diff --git a/include/powerpc/pghplus/rtems/asm.h b/include/powerpc/pghplus/rtems/asm.h
new file mode 100644
index 0000000000..e6a1df4d9f
--- /dev/null
+++ b/include/powerpc/pghplus/rtems/asm.h
@@ -0,0 +1,5 @@
+#if defined(HEADER_WARNING_DUPLICATE) /* powerpc/beatnik/rtems/asm.h */
+#warning "This header should not be included directly. (duplicate)"
+#endif
+
+#include <powerpc/beatnik/rtems/asm.h>
diff --git a/include/powerpc/pghplus/rtems/score/cpu.h b/include/powerpc/pghplus/rtems/score/cpu.h
new file mode 100644
index 0000000000..76776845ac
--- /dev/null
+++ b/include/powerpc/pghplus/rtems/score/cpu.h
@@ -0,0 +1,5 @@
+#if defined(HEADER_WARNING_DUPLICATE) /* powerpc/beatnik/rtems/score/cpu.h */
+#warning "This header should not be included directly. (duplicate)"
+#endif
+
+#include <powerpc/beatnik/rtems/score/cpu.h>
diff --git a/include/powerpc/pghplus/rtems/score/cpuatomic.h b/include/powerpc/pghplus/rtems/score/cpuatomic.h
new file mode 100644
index 0000000000..6021d1c3f4
--- /dev/null
+++ b/include/powerpc/pghplus/rtems/score/cpuatomic.h
@@ -0,0 +1,5 @@
+#if defined(HEADER_WARNING_DUPLICATE) /* arm/altcycv_devkit/rtems/score/cpuatomic.h */
+#warning "This header should not be included directly. (duplicate)"
+#endif
+
+#include <arm/altcycv_devkit/rtems/score/cpuatomic.h>
diff --git a/include/powerpc/pghplus/rtems/score/types.h b/include/powerpc/pghplus/rtems/score/types.h
new file mode 100644
index 0000000000..6382f8c184
--- /dev/null
+++ b/include/powerpc/pghplus/rtems/score/types.h
@@ -0,0 +1,5 @@
+#if defined(HEADER_WARNING_DUPLICATE) /* powerpc/beatnik/rtems/score/types.h */
+#warning "This header should not be included directly. (duplicate)"
+#endif
+
+#include <powerpc/beatnik/rtems/score/types.h>
diff --git a/include/powerpc/pghplus/tm27.h b/include/powerpc/pghplus/tm27.h
new file mode 100644
index 0000000000..a283a51568
--- /dev/null
+++ b/include/powerpc/pghplus/tm27.h
@@ -0,0 +1,5 @@
+#if defined(HEADER_WARNING_DUPLICATE) /* arm/arm1136jfs/tm27.h */
+#warning "This header should not be included directly. (duplicate)"
+#endif
+
+#include <arm/arm1136jfs/tm27.h>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 07:15:12 +0000