Add support for xilinx_zynq_zc706.

All tests build.  The other zynq BSPs have not been added yet.

8 files changed, 220 insertions, 19 deletions

diff --git a/c/wscript b/c/wscript
index 03b456b230..a9ac609844 100644
--- a/c/wscript
+++ b/c/wscript
@@ -176,11 +176,10 @@ def build(ctx):
 		install_path = ctx.env.LIBDIR
 	)
 
-
 	# First file is always installed as "linkcmds"
 	# XXX: This needs to be removed eventually by fixing the filenames.
 	if ctx.env.LINKCMDS:
-		ctx.copy(
+		ctx.copy_or_subst(
 			ctx.env.LINKCMDS[0],
 			"linkcmds",
 			"linkcmds_linkcmds"
@@ -188,8 +187,10 @@ def build(ctx):
 
 	for file in ctx.env.LINKCMDS[1:]:
 		base = basename(file)
-		ctx.copy(
+		ctx.copy_or_subst(
 			file,
 			base,
 			"linkcmds_base"
 		)
+
+
diff --git a/c/wscript_arm b/c/wscript_arm
index 42ee374d64..6ab7175e72 100644
--- a/c/wscript_arm
+++ b/c/wscript_arm
@@ -1211,23 +1211,27 @@ def stm32f4(ctx):
 
 
 
-def xilinx_zynq_a9_qemu(ctx):
+def xilinx_zynq_shared(ctx):
 	source = []
 
 	ctx.bsp.start(["src/lib/libbsp/arm/shared/start/start.S"])
 
 	source = [
-		"src/lib/libbsp/arm/shared/abort/simple_abort.c",
 		"src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c",
+		"src/lib/libbsp/arm/shared/arm-a9mpcore-smp.c",
 		"src/lib/libbsp/arm/shared/arm-cp15-set-exception-handler.c",
 		"src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c",
 		"src/lib/libbsp/arm/shared/arm-gic-irq.c",
+		"src/lib/libbsp/arm/shared/start/start.S",
 		"src/lib/libbsp/arm/shared/startup/bsp-start-memcpy.S",
 		"src/lib/libbsp/arm/xilinx-zynq/console/console-config.c",
 		"src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c",
+		"src/lib/libbsp/arm/xilinx-zynq/i2c/cadence-i2c.c",
 		"src/lib/libbsp/arm/xilinx-zynq/startup/bspreset.c",
+		"src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c",
 		"src/lib/libbsp/arm/xilinx-zynq/startup/bspstart.c",
 		"src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c",
+		"src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c",
 		"src/lib/libbsp/shared/bootcard.c",
 		"src/lib/libbsp/shared/bspclean.c",
 		"src/lib/libbsp/shared/bspgetworkarea.c",
@@ -1235,6 +1239,7 @@ def xilinx_zynq_a9_qemu(ctx):
 		"src/lib/libbsp/shared/bsppost.c",
 		"src/lib/libbsp/shared/bsppredriverhook.c",
 		"src/lib/libbsp/shared/bsppretaskinghook.c",
+		"src/lib/libbsp/shared/cpucounterdiff.c",
 		"src/lib/libbsp/shared/gnatinstallhandler.c",
 		"src/lib/libbsp/shared/sbrk.c",
 		"src/lib/libbsp/shared/src/irq-default-handler.c",
@@ -1258,7 +1263,9 @@ def xilinx_zynq_a9_qemu(ctx):
 	]
 	ctx.bsp.source(
 		source,
-		features="src_include src_include_libcpu"
+#		features="src_include src_include_libcpu"
+		features="src_include",
+        includes = ["%s/c/src/lib/libbsp/arm/shared/arm-l2c-310" % ctx.srcnode.abspath()]
 	)
 
 	source = [
@@ -1274,6 +1281,13 @@ def xilinx_zynq_a9_qemu(ctx):
 	)
 
 
+def xilinx_zynq_a9_qemu(ctx):
+	xilinx_zynq_shared(ctx)
+
+
+def xilinx_zynq_zc706(ctx):
+	xilinx_zynq_shared(ctx)
+
 
 
 def build(ctx):
@@ -1332,6 +1346,7 @@ def build(ctx):
 		"smdk2410":					smdk2410,
 		"stm32f4":					stm32f4,
 		"xilinx_zynq_a9_qemu":		xilinx_zynq_a9_qemu,
+		"xilinx_zynq_zc706":		xilinx_zynq_zc706
 	}
 
 	if not ctx.env.RTEMS_BSP in map:
diff --git a/cpukit/libcsupport/wscript b/cpukit/libcsupport/wscript
index 09031c07ed..d7523627fa 100644
--- a/cpukit/libcsupport/wscript
+++ b/cpukit/libcsupport/wscript
@@ -243,7 +243,8 @@ def build(ctx):
 		"src/cachealignedalloc.c",
 		"src/pwdgrp.c",
 		"src/getgrent.c",
-		"src/getgrnam.c"
+		"src/getgrnam.c",
+		"src/cachecoherentalloc.c"
 	]
 
 
diff --git a/cpukit/score/wscript b/cpukit/score/wscript
index 4035e930e2..1473daf5c7 100644
--- a/cpukit/score/wscript
+++ b/cpukit/score/wscript
@@ -260,7 +260,8 @@ def build(ctx):
 		"src/coretodsecondssinceepoch.c",
 		"src/coretodadjust.c",
 		"src/schedulersimplechangepriority.c",
-		"src/schedulerdefaultupdate.c"
+		"src/schedulerdefaultupdate.c",
+		"src/timespecgetasnanoseconds.c"
 	]
 
 	if ctx.env.RTEMS_ARCH == "arm":
@@ -275,7 +276,7 @@ def build(ctx):
 		]
 
 		#XXX: There needs to be a different solution for this..
-		if ctx.env.RTEMS_BSP in ["lm3s3749", "lm3s6965", "lm3s6965_qemu", "lpc17xx_ea_rom_int", "lpc17xx_plx800_ram", "lpc17xx_plx800_rom_int", "lpc17xx_ea_ram", "stm32f4", "xilinx_zynq_a9_qemu"]:
+		if ctx.env.RTEMS_BSP in ["lm3s3749", "lm3s6965", "lm3s6965_qemu", "lpc17xx_ea_rom_int", "lpc17xx_plx800_ram", "lpc17xx_plx800_rom_int", "lpc17xx_ea_ram", "stm32f4", "xilinx_zynq_a9_qemu", "xilinx_zynq_zc706"]:
 			source += [
 				"cpu/arm/armv7m-context-initialize.c",
 				"cpu/arm/armv7m-context-restore.c",
@@ -293,10 +294,10 @@ def build(ctx):
 				"cpu/arm/armv7m-isr-level-set.c",
 				"cpu/arm/armv7m-isr-vector-install.c",
 				"cpu/arm/armv7m-multitasking-start-stop.c",
-				"cpu/arm/armv7m-thread-idle.c",
+				"cpu/arm/armv7-thread-idle.c"
 			]
 
-		if ctx.env.RTEMS_BSP in ["lpc24xx_plx800_rom_int", "lpc24xx_plx800_ram", "lpc17xx_ea_rom_int", "lpc17xx_plx800_ram", "lpc17xx_plx800_rom_int", "lpc17xx_ea_ram", "raspberrypi", "realview_pbx_a9_qemu", "stm32f4", "xilinx_zynq_a9_qemu", "lpc2362", "lpc23xx_tli800", "lpc24xx_ea", "lpc24xx_ncs_ram", "lpc24xx_ncs_rom_ext", "lpc24xx_ncs_rom_int", "lpc32xx_mzx", "lpc32xx_mzx_stage_1", "lpc32xx_mzx_stage_2", "lpc32xx_phycore"]:
+		if ctx.env.RTEMS_BSP in ["lpc24xx_plx800_rom_int", "lpc24xx_plx800_ram", "lpc17xx_ea_rom_int", "lpc17xx_plx800_ram", "lpc17xx_plx800_rom_int", "lpc17xx_ea_ram", "raspberrypi", "realview_pbx_a9_qemu", "stm32f4", "xilinx_zynq_a9_qemu", "lpc2362", "lpc23xx_tli800", "lpc24xx_ea", "lpc24xx_ncs_ram", "lpc24xx_ncs_rom_ext", "lpc24xx_ncs_rom_int", "lpc32xx_mzx", "lpc32xx_mzx_stage_1", "lpc32xx_mzx_stage_2", "lpc32xx_phycore", "xilinx_zynq_zc706"]:
 			source += [
 				"cpu/arm/armv4-exception-default.S"
 			]
diff --git a/rtems_waf/configure.py b/rtems_waf/configure.py
index b6f6e30c29..3aa177c31b 100644
--- a/rtems_waf/configure.py
+++ b/rtems_waf/configure.py
@@ -7,7 +7,7 @@ from waflib.Utils import subprocess
 #		__RTEMS_SIZEOF_VOID_P__
 
 
-# BSP hacks that need to be addressed / resolved.
+# XXX: BSP hacks that need to be addressed / resolved.
 def bsp_hack(ctx, bsp):
 	if bsp == "m68k/mvme167":
 		# PowerPC unfortunatly uses macros to define this instead of an integer.
@@ -15,6 +15,11 @@ def bsp_hack(ctx, bsp):
 		ctx.define('CONSOLE_MINOR', 1)
 		ctx.define('PRINTK_MINOR', 1)
 
+	# I have no idea why it was done this way.
+	if bsp.startswith("arm/xilinx_zynq_") and ctx.env.ENABLE_SMP:
+		ctx.env.ZYNQ_CPUS = 2
+
+
 
 # general
 def config_h(ctx):
diff --git a/rtems_waf/defaults/bsp/arm.py b/rtems_waf/defaults/bsp/arm.py
index ee6a905ef8..ffb7e3dc50 100644
--- a/rtems_waf/defaults/bsp/arm.py
+++ b/rtems_waf/defaults/bsp/arm.py
@@ -591,8 +591,84 @@ class xilinx_zynq_a9_qemu(Base):
 
 	def build(self, c):
 		c.CFLAGS		= ['-march=armv7-a', '-mthumb', '-mfpu=neon', '-mfloat-abi=hard', '-mtune=cortex-a9']
-		c.LINKCMDS		= ['src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds', 'src/lib/libbsp/arm/shared/startup/linkcmds.base', 'src/lib/libbsp/arm/shared/startup/linkcmds.armv4', 'src/lib/libbsp/arm/shared/startup/linkcmds.armv7m']
+		c.LINKCMDS		= ['src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in', 'src/lib/libbsp/arm/shared/startup/linkcmds.base', 'src/lib/libbsp/arm/shared/startup/linkcmds.armv4', 'src/lib/libbsp/arm/shared/startup/linkcmds.armv7m']
 
 	def header(self, c):
 		c.BSP_START_RESET_VECTOR		= ""
 		c.BSP_ARM_A9MPCORE_PERIPHCLK	= "100000000U"
+
+
+class xilinx_zynq_shared(Base):
+
+	def build(self, c):
+		c.CFLAGS		= ['-march=armv7-a', '-mthumb', '-mfpu=neon', '-mfloat-abi=hard', '-mtune=cortex-a9']
+		c.LINKCMDS		= ['src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in', 'src/lib/libbsp/arm/shared/startup/linkcmds.base', 'src/lib/libbsp/arm/shared/startup/linkcmds.armv4', 'src/lib/libbsp/arm/shared/startup/linkcmds.armv7m']
+		c.ZYNQ_RAM_ORIGIN				= Default
+		c.ZYNQ_RAM_MMU					= Default
+		c.ZYNQ_RAM_MMU_LENGTH			= Default
+		c.ZYNQ_RAM_ORIGIN_AVAILABLE		= Default
+		c.ZYNQ_RAM_LENGTH_AVAILABLE		= Default
+		c.ZYNQ_RAM_INT_0_ORIGIN			= Default
+		c.ZYNQ_RAM_INT_0_LENGTH			= Default
+		c.ZYNQ_RAM_INT_1_ORIGIN			= Default
+		c.ZYNQ_RAM_INT_1_LENGTH			= Default
+		c.ZYNQ_CPUS						= Default
+		c.ZYNQ_RAM_NOCACHE_LENGTH		= Default
+		c.CLOCK_DRIVER_USE_FAST_IDLE	= Default
+
+
+	def header(self, c):
+		c.BSP_START_RESET_VECTOR		= Default
+		c.BSP_DATA_CACHE_ENABLED		= Default
+		c.BSP_INSTRUCTION_CACHE_ENABLED	= Default
+		c.BSP_ARM_A9MPCORE_PERIPHCLK	= Default
+		c.ZYNQ_CLOCK_UART				= Default
+		c.ZYNQ_CLOCK_CPU_1X				= Default
+	
+
+class xilinx_zynq_a9_qemu(xilinx_zynq_shared):
+	name = "arm/xilinx_zynq_a9_qemu"
+
+	def build(self, c):
+		c.CLOCK_DRIVER_USE_FAST_IDLE	= True
+		c.BSP_ZYNQ_RAM_LENGTH			= Default
+		c.ZYNQ_RAM_ORIGIN				= "0x00000000"
+		c.ZYNQ_RAM_MMU					= "0x0fffc000"
+		c.ZYNQ_RAM_ORIGIN_AVAILABLE		= "%(ZYNQ_RAM_ORIGIN)s"
+		c.ZYNQ_RAM_LENGTH_AVAILABLE		= "%(BSP_ZYNQ_RAM_LENGTH)s - 16k"
+
+	def header(self, c):
+		c.BSP_DATA_CACHE_ENABLED = False
+
+
+class xilinx_zynq_zc702(xilinx_zynq_shared):
+	name = "arm/xilinx_zynq_zc702"
+
+	def build(self, c):
+		c.BSP_ARM_A9MPCORE_PERIPHCLK	= "333333333U"
+		c.ZYNQ_RAM_ORIGIN				= "0x00100000"
+
+	def header(self, c):
+		c.ZYNQ_CLOCK_UART				= "50000000UL"
+		c.BSP_ZYNQ_RAM_LENGTH			= "1024M"
+
+
+class xilinx_zynq_zc706(xilinx_zynq_shared):
+	name = "arm/xilinx_zynq_zc706"
+
+	def build(self, c):
+		c.BSP_ZYNQ_RAM_LENGTH			= "1024M"
+		c.ZYNQ_RAM_LENGTH_AVAILABLE		= "%(BSP_ZYNQ_RAM_LENGTH)s - 4M - 16k"
+
+
+class xilinx_zynq_zedboard(xilinx_zynq_shared):
+	name = "arm/xilinx_zynq_zedboard"
+
+	def build(self, c):
+		c.BSP_ZYNQ_RAM_LENGTH			= "512M"
+		c.ZYNQ_RAM_ORIGIN				= "0x00100000"
+
+	def header(self, c):
+		c.BSP_ARM_A9MPCORE_PERIPHCLK	= "666666667U"
+		c.ZYNQ_CLOCK_UART				= "50000000UL"
+
diff --git a/rtems_waf/defaults/options.py b/rtems_waf/defaults/options.py
index 6c940a7a76..019d93139d 100644
--- a/rtems_waf/defaults/options.py
+++ b/rtems_waf/defaults/options.py
@@ -2220,6 +2220,7 @@ class MPC55XX_CONSOLE_MINOR(Integer):
 
 class MPC55XX_BOARD_MPC5674F_RSM6(Boolean):
 	value = True
+	quote = False
 	undef = True
 	descr = "if defined, use custom settings for RSM6 board"
 
@@ -2245,3 +2246,82 @@ class MPC83XX_BOARD_MPC8309SOM(Boolean):
 	value = True
 	undef = True
 	descr = "if defined, then use settings for the MPC8309SOM board"
+
+
+class ZYNQ_RAM_ORIGIN(String):
+	value = "0x00400000"
+	undef = True
+	descr = "Normal RAM region origin"
+
+class ZYNQ_RAM_MMU(String):
+	value = "%(ZYNQ_RAM_ORIGIN)s"
+	quote = False
+	undef = True
+	descr = "MMU region origin"
+
+class ZYNQ_RAM_MMU_LENGTH(String):
+	value = "16k"
+	undef = True
+	descr = "MMU region length"
+
+class ZYNQ_RAM_ORIGIN_AVAILABLE(String):
+	value = "%(ZYNQ_RAM_ORIGIN)s + 0x00004000"
+	undef = True
+	descr = "Origin of available RAM"
+
+class ZYNQ_RAM_LENGTH_AVAILABLE(String):
+	value = "%(BSP_ZYNQ_RAM_LENGTH)s - 1M - 16k"
+	undef = True
+	descr = "Length of available RAM"
+
+class ZYNQ_RAM_INT_0_ORIGIN(String):
+	value = "0x00000000"
+	undef = True
+	descr = "Internal 0 RAM region origin"
+
+class ZYNQ_RAM_INT_0_LENGTH(String):
+	value = "64k + 64k + 64k"
+	undef = True
+	descr = "Internal 0 RAM region length"
+
+class ZYNQ_RAM_INT_1_ORIGIN(String):
+	value = "0xFFFF0000"
+	undef = True
+	descr = "Internal 1 RAM region origin"
+
+class ZYNQ_RAM_INT_1_LENGTH(String):
+	value = "64k - 512"
+	undef = True
+	descr = "Internal 1 RAM region length"
+
+class BSP_ZYNQ_RAM_LENGTH(String):
+	value = "256M"
+	quote = False
+	undef = True
+	descr = "Override a BSP's default RAM length"
+
+class ZYNQ_RAM_NOCACHE_LENGTH(String):
+	value = "1M"
+	quote = False
+	undef = True
+	descr = "Length of nocache RAM region"
+
+class ZYNQ_CLOCK_CPU_1X(String):
+	value = "111111111U"
+	quote = False
+	undef = True
+	descr = "Zynq cpu_1x clock frequency in Hz"
+
+class ZYNQ_CLOCK_UART(String):
+	value = "50000000UL"
+	quote = False
+	undef = True
+	descr = "Zynq UART clock frequency in Hz"
+
+
+class ZYNQ_CPUS(Integer):
+	value = 1
+	quote = False
+	undef = True
+	descr = "Number of active cores"
+
diff --git a/rtems_waf/waf.py b/rtems_waf/waf.py
index 2a3595044f..9f8a1112db 100644
--- a/rtems_waf/waf.py
+++ b/rtems_waf/waf.py
@@ -101,12 +101,34 @@ def rtems_program(ctx, target_name, source, **kwarg):
 
 @conf
 def copy(ctx, source, target, name):
-	ctx(
-		rule='cp ${SRC} ${TGT}', # XXX: Make something that works on windows.
-		source=source,
-		target=target,
-		name=name
-	)
+		ctx(
+			rule='cp ${SRC} ${TGT}', # XXX: Make something that works on windows.
+			source=source,
+			target=target,
+			name=name
+		)
+
+@conf
+def copy_or_subst(ctx, source, target, name):
+	if source.endswith(".in"):
+		# This is required as not all 'linkcmd' files are named as such see the
+		# bottom of c/wscript  It can be removed when the names are normalised
+		# XXX: fix 'linkcmd' names.
+
+		if target.endswith(".in"):
+			target = target[:-3]
+
+		ctx(
+			features	= 'subst',
+			source		= source,
+			target		=  target,
+			encoding	= 'ascii', # for python3.
+			name		= name,
+#			is_copy		= True
+		)
+	else:
+		ctx.copy(source, target, name)
+
 
 #################
 # Configure Steps