From e43994dfbb2c0ce9012c33c64f14533acc230366 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 27 Jun 2018 10:05:50 +0200 Subject: riscv: Optimize context switch and interrupts Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433. --- cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 26 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'cpukit/score/cpu/riscv/include/rtems/score/cpu.h') diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 61d3ffa3f7..888de27e8e 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -105,17 +105,31 @@ extern "C" { #ifndef ASM typedef struct { - /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/ - unsigned long x[32]; - - uint32_t isr_dispatch_disable; #ifdef RTEMS_SMP - volatile bool is_executing; + volatile uint32_t is_executing; +#else + uint32_t reserved; #endif + uint32_t isr_dispatch_disable; + uintptr_t ra; + uintptr_t sp; + uintptr_t tp; + uintptr_t s0; + uintptr_t s1; + uintptr_t s2; + uintptr_t s3; + uintptr_t s4; + uintptr_t s5; + uintptr_t s6; + uintptr_t s7; + uintptr_t s8; + uintptr_t s9; + uintptr_t s10; + uintptr_t s11; } Context_Control; #define _CPU_Context_Get_SP( _context ) \ - (_context)->x[2] + (_context)->sp typedef struct { /** TODO FPU registers are listed here */ -- cgit v1.2.3