From f22bba3cb43182374bbddfad4e28545f89bd14ed Mon Sep 17 00:00:00 2001 From: Eugeniy Meshcheryakov Date: Fri, 26 Apr 2013 11:03:59 +0200 Subject: bsp/lm3s69xx: New BSP variants Add support for LM3S3749. --- c/src/lib/libbsp/arm/lm3s69xx/Makefile.am | 10 +- c/src/lib/libbsp/arm/lm3s69xx/configure.ac | 36 ++- .../libbsp/arm/lm3s69xx/console/console-config.c | 13 +- c/src/lib/libbsp/arm/lm3s69xx/console/uart.c | 28 ++ c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h | 10 +- c/src/lib/libbsp/arm/lm3s69xx/include/io.h | 147 +++++++++ c/src/lib/libbsp/arm/lm3s69xx/include/irq.h | 100 +++--- c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h | 358 ++++++++++++++++++++- c/src/lib/libbsp/arm/lm3s69xx/include/ssi.h | 27 ++ c/src/lib/libbsp/arm/lm3s69xx/include/syscon.h | 26 ++ c/src/lib/libbsp/arm/lm3s69xx/include/uart.h | 56 ---- .../libbsp/arm/lm3s69xx/make/custom/lm3s3749.cfg | 5 + .../arm/lm3s69xx/make/custom/lm3s6965_qemu.cfg | 5 + c/src/lib/libbsp/arm/lm3s69xx/preinstall.am | 12 + c/src/lib/libbsp/arm/lm3s69xx/ssi/ssi.c | 170 ++++++++++ c/src/lib/libbsp/arm/lm3s69xx/startup/bspreset.c | 8 +- c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c | 101 +++++- c/src/lib/libbsp/arm/lm3s69xx/startup/io.c | 144 +++++++++ .../libbsp/arm/lm3s69xx/startup/linkcmds.lm3s3749 | 28 ++ .../libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965 | 4 +- .../arm/lm3s69xx/startup/linkcmds.lm3s6965_qemu | 28 ++ c/src/lib/libbsp/arm/lm3s69xx/startup/syscon.c | 106 ++++++ 22 files changed, 1286 insertions(+), 136 deletions(-) create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/include/io.h create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/include/ssi.h create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/include/syscon.h create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749.cfg create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965_qemu.cfg create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/ssi/ssi.c create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/startup/io.c create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s3749 create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965_qemu create mode 100644 c/src/lib/libbsp/arm/lm3s69xx/startup/syscon.c diff --git a/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am b/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am index b6ff658b95..6d2ad7f285 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am @@ -18,7 +18,7 @@ project_lib_DATA = project_lib_DATA += start.$(OBJEXT) project_lib_DATA += startup/linkcmds -EXTRA_DIST = startup/linkcmds.lm3s6965 +EXTRA_DIST = startup/linkcmds.lm3s6965 startup/linkcmds.lm3s6965_qemu startup/linkcmds.lm3s3749 ############################################################################### # Header # @@ -45,6 +45,9 @@ include_bsp_HEADERS += ../shared/include/start.h include_bsp_HEADERS += ../shared/armv7m/include/armv7m-irq.h include_bsp_HEADERS += include/irq.h include_bsp_HEADERS += include/uart.h +include_bsp_HEADERS += include/io.h +include_bsp_HEADERS += include/syscon.h +include_bsp_HEADERS += include/ssi.h include_bsp_HEADERS += include/lm3s69xx.h ############################################################################### @@ -75,6 +78,8 @@ libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S libbsp_a_SOURCES += startup/bspstart.c libbsp_a_SOURCES += startup/bspstarthook.c libbsp_a_SOURCES += startup/bspreset.c +libbsp_a_SOURCES += startup/io.c +libbsp_a_SOURCES += startup/syscon.c # IRQ libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c @@ -107,6 +112,9 @@ libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += ../../../libcpu/arm/shared/cache/cache_.h libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include +# SSI +libbsp_a_SOURCES += ssi/ssi.c + ############################################################################### # Special Rules # ############################################################################### diff --git a/c/src/lib/libbsp/arm/lm3s69xx/configure.ac b/c/src/lib/libbsp/arm/lm3s69xx/configure.ac index 82f9a7a9b2..833c56d3f9 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/configure.ac +++ b/c/src/lib/libbsp/arm/lm3s69xx/configure.ac @@ -21,13 +21,21 @@ RTEMS_PROG_CCAS RTEMS_CHECK_NETWORKING AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") -RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*],[]) +RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*_qemu],[]) +RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_SMALL_MEMORY],[disable testsuite samples with high memory demands]) -RTEMS_BSPOPTS_SET([LM3S69XX_SYSTEM_CLOCK],[*],[50000000]) +RTEMS_BSPOPTS_SET([LM3S69XX_SYSTEM_CLOCK],[*],[50000000U]) RTEMS_BSPOPTS_HELP([LM3S69XX_SYSTEM_CLOCK],[system clock in Hz]) -RTEMS_BSPOPTS_SET([LM3S69XX_UART_BAUD],[*],[115200]) +RTEMS_BSPOPTS_SET([LM3S69XX_XTAL_CONFIG],[lm3s6965*],[0xE]) dnl 8MHz XTAL +RTEMS_BSPOPTS_SET([LM3S69XX_XTAL_CONFIG],[lm3s3749*],[0x10]) dnl 10MHz XTAL +RTEMS_BSPOPTS_HELP([LM3S69XX_XTAL_CONFIG],[crystal configuration for RCC register]) + +RTEMS_BSPOPTS_SET([LM3S69XX_SSI_CLOCK],[*],[1000000U]) +RTEMS_BSPOPTS_HELP([LM3S69XX_SSI_CLOCK],[SSI clock in Hz]) + +RTEMS_BSPOPTS_SET([LM3S69XX_UART_BAUD],[*],[115200U]) RTEMS_BSPOPTS_HELP([LM3S69XX_UART_BAUD],[baud for UARTs]) RTEMS_BSPOPTS_SET([LM3S69XX_ENABLE_UART_0],[*],[1]) @@ -39,6 +47,28 @@ RTEMS_BSPOPTS_HELP([LM3S69XX_ENABLE_UART_1],[enable UART 1]) RTEMS_BSPOPTS_SET([LM3S69XX_ENABLE_UART_2],[*],[]) RTEMS_BSPOPTS_HELP([LM3S69XX_ENABLE_UART_2],[enable UART 2]) +RTEMS_BSPOPTS_SET([LM3S69XX_NUM_GPIO_BLOCKS],[lm3s3749*],[8]) +RTEMS_BSPOPTS_SET([LM3S69XX_NUM_GPIO_BLOCKS],[lm3s6965*],[7]) +RTEMS_BSPOPTS_HELP([LM3S69XX_NUM_GPIO_BLOCKS],[number of GPIO blocks supported by MCU]) + +RTEMS_BSPOPTS_SET([LM3S69XX_NUM_SSI_BLOCKS],[lm3s3749*],[2]) +RTEMS_BSPOPTS_SET([LM3S69XX_NUM_SSI_BLOCKS],[lm3s6965*],[1]) +RTEMS_BSPOPTS_HELP([LM3S69XX_NUM_SSI_BLOCKS],[number of SSI blocks supported by MCU]) + +RTEMS_BSPOPTS_SET([LM3S69XX_HAS_UDMA],[lm3s3749*],[1]) +RTEMS_BSPOPTS_SET([LM3S69XX_HAS_UDMA],[*],[0]) +RTEMS_BSPOPTS_HELP([LM3S69XX_HAS_UDMA],[defined if MCU supports UDMA]) + +RTEMS_BSPOPTS_SET([LM3S69XX_USE_AHB_FOR_GPIO],[lm3s3749*],[1]) +RTEMS_BSPOPTS_SET([LM3S69XX_USE_AHB_FOR_GPIO],[*],[0]) +RTEMS_BSPOPTS_HELP([LM3S69XX_USE_AHB_FOR_GPIO],[use AHB apperture to access GPIO registers]) + +RTEMS_BSPOPTS_SET([LM3S69XX_MCU_LM3S3749],[lm3s3749*],[1]) +RTEMS_BSPOPTS_HELP([LM3S69XX_MCU_LM3S3749],[board has LM3S3749 MCU]) + +RTEMS_BSPOPTS_SET([LM3S69XX_MCU_LM3S6965],[lm3s6965*],[1]) +RTEMS_BSPOPTS_HELP([LM3S69XX_MCU_LM3S6965],[board has LM3S6965 MCU]) + RTEMS_BSP_CLEANUP_OPTIONS(0, 0) RTEMS_BSP_LINKCMDS diff --git a/c/src/lib/libbsp/arm/lm3s69xx/console/console-config.c b/c/src/lib/libbsp/arm/lm3s69xx/console/console-config.c index e0c79b8090..474c02a92c 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/console/console-config.c +++ b/c/src/lib/libbsp/arm/lm3s69xx/console/console-config.c @@ -1,4 +1,6 @@ /* + * Copyright © 2013 Eugeniy Meshcheryakov + * * Copyright (c) 2011 Sebastian Huber. All rights reserved. * * embedded brains GmbH @@ -29,7 +31,8 @@ console_tbl Console_Configuration_Ports [] = { .pDeviceFns = &lm3s69xx_uart_fns, .ulCtrlPort1 = LM3S69XX_UART_0_BASE, .ulClock = LM3S69XX_UART_BAUD, - .ulIntVector = LM3S69XX_IRQ_UART_0 + .ulIntVector = LM3S69XX_IRQ_UART_0, + .pDeviceParams = (void *)0 }, #endif #ifdef LM3S69XX_ENABLE_UART_1 @@ -39,7 +42,8 @@ console_tbl Console_Configuration_Ports [] = { .pDeviceFns = &lm3s69xx_uart_fns, .ulCtrlPort1 = LM3S69XX_UART_1_BASE, .ulClock = LM3S69XX_UART_BAUD, - .ulIntVector = LM3S69XX_IRQ_UART_1 + .ulIntVector = LM3S69XX_IRQ_UART_1, + .pDeviceParams = (void *)1 } #endif #ifdef LM3S69XX_ENABLE_UART_2 @@ -49,7 +53,8 @@ console_tbl Console_Configuration_Ports [] = { .pDeviceFns = &lm3s69xx_uart_fns, .ulCtrlPort1 = LM3S69XX_UART_2_BASE, .ulClock = LM3S69XX_UART_BAUD, - .ulIntVector = LM3S69XX_IRQ_UART_2 + .ulIntVector = LM3S69XX_IRQ_UART_2, + .pDeviceParams = (void *)2 } #endif }; @@ -64,7 +69,7 @@ static void output_char(char c) { const console_fns *con = Console_Configuration_Ports [Console_Port_Minor].pDeviceFns; - + if (c == '\n') { con->deviceWritePolled((int) Console_Port_Minor, '\r'); } diff --git a/c/src/lib/libbsp/arm/lm3s69xx/console/uart.c b/c/src/lib/libbsp/arm/lm3s69xx/console/uart.c index cc51c83c47..4d916662c2 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/console/uart.c +++ b/c/src/lib/libbsp/arm/lm3s69xx/console/uart.c @@ -1,4 +1,6 @@ /* + * Copyright © 2013 Eugeniy Meshcheryakov + * * Copyright (c) 2011 Sebastian Huber. All rights reserved. * * embedded brains GmbH @@ -15,6 +17,8 @@ #include #include #include +#include +#include static volatile lm3s69xx_uart *get_uart_regs(int minor) { @@ -23,11 +27,35 @@ static volatile lm3s69xx_uart *get_uart_regs(int minor) return (lm3s69xx_uart *) ct->ulCtrlPort1; } +static unsigned int get_uart_number(int minor) +{ + console_tbl *ct = Console_Port_Tbl [minor]; + + return (unsigned int)ct->pDeviceParams; +} + +/* + * Returns both integer and fractional parts as one number. + */ +static uint32_t get_baud_div(uint32_t baud) +{ + uint32_t clock4 = LM3S69XX_SYSTEM_CLOCK * 4; + return (clock4 + baud - 1) / baud; +} + static void initialize(int minor) { volatile lm3s69xx_uart *uart = get_uart_regs(minor); + unsigned int num = get_uart_number(minor); + + lm3s69xx_syscon_enable_uart_clock(num, true); uart->ctl = 0; + + uint32_t brd = get_baud_div(LM3S69XX_UART_BAUD); + uart->ibrd = brd / 64; + uart->fbrd = brd % 64; + uart->lcrh = UARTLCRH_WLEN(0x3) | UARTLCRH_FEN; uart->ctl = UARTCTL_RXE | UARTCTL_TXE | UARTCTL_UARTEN; } diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h b/c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h index 789b88f51c..a385cb423f 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h +++ b/c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h @@ -23,6 +23,8 @@ #define BSP_ARMV7M_SYSTICK_PRIORITY (6 << 5) +#define BSP_ARMV7M_SYSTICK_FREQUENCY LM3S69XX_SYSTEM_CLOCK + #ifndef ASM #include @@ -31,14 +33,6 @@ #include #include -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - #endif /* ASM */ #endif /* LIBBSP_ARM_LM3S69XX_BSP_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/io.h b/c/src/lib/libbsp/arm/lm3s69xx/include/io.h new file mode 100644 index 0000000000..4b7f920e01 --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/include/io.h @@ -0,0 +1,147 @@ +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_IO_H +#define LIBBSP_ARM_LM3S69XX_IO_H +#include +#include + +typedef enum { + LM3S69XX_GPIO_DIRECTION_INPUT, + LM3S69XX_GPIO_DIRECTION_OUTPUT +} lm3s69xx_gpio_direction; + +typedef enum { + LM3S69XX_GPIO_OTYPE_PUSH_PULL, + LM3S69XX_GPIO_OTYPE_OPEN_DRAIN +} lm3s69xx_gpio_otype; + +typedef enum { + LM3S69XX_GPIO_DRIVE_2MA, + LM3S69XX_GPIO_DRIVE_4MA, + LM3S69XX_GPIO_DRIVE_8MA +} lm3s69xx_gpio_drive; + +typedef enum { + LM3S69XX_GPIO_NO_PULL, + LM3S69XX_GPIO_PULL_UP, + LM3S69XX_GPIO_PULL_DOWN +} lm3s69xx_gpio_pull; + +typedef enum { + LM3S69XX_GPIO_DIGITAL_DISABLE, + LM3S69XX_GPIO_DIGITAL_ENABLE, +} lm3s69xx_gpio_digital; + +typedef enum { + LM3S69XX_GPIO_AF_DISABLE, + LM3S69XX_GPIO_AF_ENABLE +} lm3s69xx_gpio_af; + +typedef enum { + LM3S69XX_GPIO_ANALOG_DISABLE, + LM3S69XX_GPIO_ANALOG_ENABLE +} lm3s69xx_gpio_analog; + +typedef enum { + LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL, + LM3S69XX_GPIO_SLEW_RATE_CONTROL +} lm3s69xx_gpio_slew_rate_control; + +typedef struct { + unsigned int pin_first : 8; + unsigned int pin_last : 8; + unsigned int digital : 1; + unsigned int alternate : 1; + unsigned int analog : 1; + unsigned int dir : 1; + unsigned int otype : 1; + unsigned int drive : 2; + unsigned int pull : 2; + unsigned int slr : 1; +} lm3s69xx_gpio_config; + +typedef enum { + LM3S69XX_PORT_A, + LM3S69XX_PORT_B, + LM3S69XX_PORT_C, + LM3S69XX_PORT_D, + LM3S69XX_PORT_E, + LM3S69XX_PORT_F, + LM3S69XX_PORT_G, +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 + LM3S69XX_PORT_H +#endif +} lm3s69xx_gpio_port; + +#define LM3S69XX_GPIO_PIN(port, idx) (((port) << 3) | (idx)) +#define LM3S69XX_GPIO_PORT_OF_PIN(pin) (((pin) >> 3) & 0xf) +#define LM3S69XX_GPIO_INDEX_OF_PIN(pin) ((pin) & 0x7) + +#define LM3S69XX_PIN_UART_TX(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_UART_RX(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_INPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_PULL_UP, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_LED(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_DISABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_8MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_SSI_TX(port, idx) LM3S69XX_PIN_UART_TX(port, idx) +#define LM3S69XX_PIN_SSI_RX(port, idx) LM3S69XX_PIN_UART_RX(port, idx) + +#ifdef __cplusplus +extern "C" { +#endif + +void lm3s69xx_gpio_set_config(const lm3s69xx_gpio_config *config); +void lm3s69xx_gpio_set_config_array(const lm3s69xx_gpio_config *configs, unsigned int count); +void lm3s69xx_gpio_digital_enable(unsigned int pin, bool enable); +void lm3s69xx_gpio_analog_mode_select(unsigned int pin, bool enable); + +void lm3s69xx_gpio_set_pin(unsigned int pin, bool set); +bool lm3s69xx_gpio_get_pin(unsigned int pin); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_IO_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/irq.h b/c/src/lib/libbsp/arm/lm3s69xx/include/irq.h index b6914e287a..00b570e57e 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/irq.h +++ b/c/src/lib/libbsp/arm/lm3s69xx/include/irq.h @@ -1,4 +1,6 @@ /* + * Copyright © 2013 Eugeniy Meshcheryakov + * * Copyright (c) 2011 Sebastian Huber. All rights reserved. * * embedded brains GmbH @@ -20,54 +22,61 @@ #include #include #include +#include + +#endif /* ASM */ -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ +#define LM3S69XX_IRQ_GPIO_PORT_A 0 +#define LM3S69XX_IRQ_GPIO_PORT_B 1 +#define LM3S69XX_IRQ_GPIO_PORT_C 2 +#define LM3S69XX_IRQ_GPIO_PORT_D 3 +#define LM3S69XX_IRQ_GPIO_PORT_E 4 +#define LM3S69XX_IRQ_UART_0 5 +#define LM3S69XX_IRQ_UART_1 6 +#define LM3S69XX_IRQ_SSI_0 7 +#define LM3S69XX_IRQ_I2C_0 8 +#define LM3S69XX_IRQ_PWM_FAULT 9 +#define LM3S69XX_IRQ_PWM_GENERATOR_0 10 +#define LM3S69XX_IRQ_PWM_GENERATOR_1 11 +#define LM3S69XX_IRQ_PWM_GENERATOR_2 12 +#define LM3S69XX_IRQ_QEI_0 13 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_0 14 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_1 15 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_2 16 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_3 17 +#define LM3S69XX_IRQ_WATCHDOG_TIMER_0 18 +#define LM3S69XX_IRQ_TIMER_0_A 19 +#define LM3S69XX_IRQ_TIMER_0_B 20 +#define LM3S69XX_IRQ_TIMER_1_A 21 +#define LM3S69XX_IRQ_TIMER_1_B 22 +#define LM3S69XX_IRQ_TIMER_2_A 23 +#define LM3S69XX_IRQ_TIMER_2_B 24 +#define LM3S69XX_IRQ_ANALOG_COMPARATOR_0 25 +#define LM3S69XX_IRQ_ANALOG_COMPARATOR_1 26 +#define LM3S69XX_IRQ_SYSTEM_CONTROL 28 +#define LM3S69XX_IRQ_FLASH_MEMORY_CONTROL 29 +#define LM3S69XX_IRQ_GPIO_PORT_F 30 +#define LM3S69XX_IRQ_GPIO PORT_G 31 +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_GPIO PORT_H 32 +#define LM3S69XX_IRQ_UART_2 33 +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_SSI_1 34 +#define LM3S69XX_IRQ_TIMER_3_A 35 +#define LM3S69XX_IRQ_TIMER_3_B 36 +#define LM3S69XX_IRQ_I2C_1 37 -#ifdef __cplusplus -} -#endif /* __cplusplus */ +/* NOTE: lm3s6965 */ +#define LM3S69XX_IRQ_QEI_1 38 +#define LM3S69XX_IRQ_ETHERNET_CONTROLLER 42 -#endif /* ASM */ +#define LM3S69XX_IRQ_HIBERNATION_MODULE 43 -#define LM3S69XX_IRQ_GPIO_PORT_A 16 -#define LM3S69XX_IRQ_GPIO_PORT_B 17 -#define LM3S69XX_IRQ_GPIO_PORT_C 18 -#define LM3S69XX_IRQ_GPIO_PORT_D 19 -#define LM3S69XX_IRQ_GPIO_PORT_E 20 -#define LM3S69XX_IRQ_UART_0 21 -#define LM3S69XX_IRQ_UART_1 22 -#define LM3S69XX_IRQ_SSI_0 23 -#define LM3S69XX_IRQ_I2C_0 24 -#define LM3S69XX_IRQ_PWM_GENERATOR_0 26 -#define LM3S69XX_IRQ_PWM_GENERATOR_1 27 -#define LM3S69XX_IRQ_PWM_GENERATOR_2 28 -#define LM3S69XX_IRQ_QEI_0 29 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_0 30 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_1 31 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_2 32 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_3 33 -#define LM3S69XX_IRQ_WATCHDOG_TIMER_0 34 -#define LM3S69XX_IRQ_TIMER_0_A 35 -#define LM3S69XX_IRQ_TIMER_0_B 36 -#define LM3S69XX_IRQ_TIMER_1_A 37 -#define LM3S69XX_IRQ_TIMER_1_B 38 -#define LM3S69XX_IRQ_TIMER_2_A 39 -#define LM3S69XX_IRQ_TIMER_2_B 40 -#define LM3S69XX_IRQ_ANALOG_COMPARATOR_0 41 -#define LM3S69XX_IRQ_ANALOG_COMPARATOR_1 42 -#define LM3S69XX_IRQ_SYSTEM_CONTROL 44 -#define LM3S69XX_IRQ_FLASH_MEMORY_CONTROL 45 -#define LM3S69XX_IRQ_GPIO_PORT_F 46 -#define LM3S69XX_IRQ_GPIO PORT_G 47 -#define LM3S69XX_IRQ_UART_2 49 -#define LM3S69XX_IRQ_TIMER_3_A 51 -#define LM3S69XX_IRQ_TIMER_3_B 52 -#define LM3S69XX_IRQ_I2C_1 53 -#define LM3S69XX_IRQ_QEI_1 54 -#define LM3S69XX_IRQ_ETHERNET_CONTROLLER 58 -#define LM3S69XX_IRQ_HIBERNATION_MODULE 59 +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_USB 44 +#define LM3S69XX_IRQ_PWM_GENERATOR_3 45 +#define LM3S69XX_IRQ_UDMA_SOFTWARE 46 +#define LM3S69XX_IRQ_UDMA_ERROR 47 #define LM3S69XX_IRQ_PRIORITY_VALUE_MIN 0 #define LM3S69XX_IRQ_PRIORITY_VALUE_MAX 7 @@ -76,6 +85,7 @@ extern "C" { #define LM3S69XX_IRQ_PRIORITY_LOWEST LM3S69XX_IRQ_PRIORITY_VALUE_MAX #define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX 59 +/* NOTE: for lm3s6965 - 43 */ +#define BSP_INTERRUPT_VECTOR_MAX 47 #endif /* LIBBSP_ARM_LM3S69XX_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h b/c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h index 5f66b7e746..7d54c25a0b 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h +++ b/c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h @@ -1,4 +1,6 @@ /* + * Copyright © 2013 Eugeniy Meshcheryakov + * * Copyright (c) 2011 Sebastian Huber. All rights reserved. * * embedded brains GmbH @@ -14,17 +16,361 @@ #ifndef LIBBSP_ARM_LM3S69XX_LM3S69XX_H #define LIBBSP_ARM_LM3S69XX_LM3S69XX_H +#include +#include -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ +#define LM3S69XX_SYSCON_BASE 0x400fe000 #define LM3S69XX_UART_0_BASE 0x4000c000 #define LM3S69XX_UART_1_BASE 0x4000d000 #define LM3S69XX_UART_2_BASE 0x4000e000 -#ifdef __cplusplus -} -#endif /* __cplusplus */ +#ifdef LM3S69XX_USE_AHB_FOR_GPIO +#define LM3S69XX_GPIO_A_BASE 0x40058000 +#define LM3S69XX_GPIO_B_BASE 0x40059000 +#define LM3S69XX_GPIO_C_BASE 0x4005a000 +#define LM3S69XX_GPIO_D_BASE 0x4005b000 +#define LM3S69XX_GPIO_E_BASE 0x4005c000 +#define LM3S69XX_GPIO_F_BASE 0x4005d000 +#define LM3S69XX_GPIO_G_BASE 0x4005e000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define LM3S69XX_GPIO_H_BASE 0x4005f000 +#endif + +#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(LM3S69XX_GPIO_A_BASE + (port) * 0x1000)) +#else /* LM3S69XX_USE_AHB_FOR_GPIO */ +#define LM3S69XX_GPIO_A_BASE 0x40004000 +#define LM3S69XX_GPIO_B_BASE 0x40005000 +#define LM3S69XX_GPIO_C_BASE 0x40006000 +#define LM3S69XX_GPIO_D_BASE 0x40007000 +#define LM3S69XX_GPIO_E_BASE 0x40024000 +#define LM3S69XX_GPIO_F_BASE 0x40025000 +#define LM3S69XX_GPIO_G_BASE 0x40026000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define LM3S69XX_GPIO_H_BASE 0x40027000 +#endif + +#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(((port) < 4) ? \ + (LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \ + (LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000))) +#endif /* LM3S69XX_USE_AHB_FOR_GPIO */ + +#define LM3S69XX_SSI_0_BASE 0x40008000 +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +#define LM3S69XX_SSI_1_BASE 0x40009000 +#endif + +#define LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE) + +#define LM3S69XX_PLL_FREQUENCY 400000000U + +typedef struct { + uint32_t data[256]; /* Masked data registers are included here. */ + uint32_t dir; + uint32_t is; + uint32_t ibe; + uint32_t iev; + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t afsel; + + uint32_t reserved_0[55]; + + uint32_t dr2r; + uint32_t dr4r; + uint32_t dr8r; + uint32_t odr; + uint32_t pur; + uint32_t pdr; + uint32_t slr; + uint32_t den; + uint32_t lock; + uint32_t cr; + uint32_t amsel; +} lm3s69xx_gpio; + +typedef struct { + uint32_t did0; + uint32_t did1; + + uint32_t dc0; + uint32_t reserved_0; + uint32_t dc1; + uint32_t dc2; + uint32_t dc3; + uint32_t dc4; + uint32_t dc5; + uint32_t dc6; + uint32_t dc7; + + uint32_t reserved_1; + +#define SYSCONPBORCTL_BORIOR BSP_BIT32(1) + uint32_t pborctl; + +#define SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5) +#define SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5) + uint32_t ldopctl; + + uint32_t reserved_2[2]; + + uint32_t srcr0; + uint32_t srcr1; + uint32_t srcr2; + + uint32_t reserved_3; + +#define SYSCONRIS_MOSCPUPRIS BSP_BIT32(8) +#define SYSCONRIS_USBPLLRIS BSP_BIT32(7) +#define SYSCONRIS_PLLLRIS BSP_BIT32(6) +#define SYSCONRIS_BORRIS BSP_BIT32(1) + uint32_t ris; + +#define SYSCONIMC_MOSCPUPIM BSP_BIT32(8) +#define SYSCONIMC_USBPLLLIM BSP_BIT32(7) +#define SYSCONIMC_PLLLIM BSP_BIT32(6) +#define SYSCONIMC_BORIM BSP_BIT32(1) + uint32_t imc; + +#define SYSCONMISC_MOSCPUPMIS BSP_BIT32(8) +#define SYSCONMISC_USBPLLLMIS BSP_BIT32(7) +#define SYSCONMISC_PLLLMIS BSP_BIT32(6) +#define SYSCONMISC_BORMIS BSP_BIT32(1) + uint32_t misc; + +#define SYSCONRESC_MOSCFAIL BSP_BIT32(16) +#define SYSCONRESC_SW BSP_BIT32(4) +#define SYSCONRESC_WDT BSP_BIT32(3) +#define SYSCONRESC_BOR BSP_BIT32(2) +#define SYSCONRESC_POR BSP_BIT32(1) +#define SYSCONRESC_EXT BSP_BIT32(0) + uint32_t resc; + +#define SYSCONRCC_AGC BSP_BIT32(27) +#define SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26) +#define SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26) +#define SYSCONRCC_USESYSDIV BSP_BIT32(22) +#define SYSCONRCC_USEPWMDIV BSP_BIT32(20) +#define SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19) +#define SYSCONRCC_PWMDIV_DIV2_VAL 0 +#define SYSCONRCC_PWMDIV_DIV4_VAL 1 +#define SYSCONRCC_PWMDIV_DIV8_VAL 2 +#define SYSCONRCC_PWMDIV_DIV16_VAL 3 +#define SYSCONRCC_PWMDIV_DIV32_VAL 4 +#define SYSCONRCC_PWMDIV_DIV64_VAL 5 +#define SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19) +#define SYSCONRCC_PWRDN BSP_BIT32(13) +#define SYSCONRCC_BYPASS BSP_BIT32(11) +#define SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10) +#define SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10) +#define SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5) +#define SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0) +#define SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1) +#define SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2) +#define SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3) +#define SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5) +#define SYSCONRCC_IOSCDIS BSP_BIT32(1) +#define SYSCONRCC_MOSCDIS BSP_BIT32(0) + uint32_t rcc; + +#define SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13) +#define SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13) +#define SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4) +#define SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4) + uint32_t pllcfg; + + uint32_t reserved_4; + +#define SYSCONGPIOHBCTL_PORTH BSP_BIT32(7) +#define SYSCONGPIOHBCTL_PORTG BSP_BIT32(6) +#define SYSCONGPIOHBCTL_PORTF BSP_BIT32(5) +#define SYSCONGPIOHBCTL_PORTE BSP_BIT32(4) +#define SYSCONGPIOHBCTL_PORTD BSP_BIT32(3) +#define SYSCONGPIOHBCTL_PORTC BSP_BIT32(2) +#define SYSCONGPIOHBCTL_PORTB BSP_BIT32(1) +#define SYSCONGPIOHBCTL_PORTA BSP_BIT32(0) + uint32_t gpiohbctl; + +#define SYSCONRCC2_USERCC2 BSP_BIT32(31) +#define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28) +#define SYSCONRCC2_SYSDIV2_MSK(val) BSP_MSK32(23, 28) +#define SYSCONRCC2_USBPWRDN BSP_BIT32(14) +#define SYSCONRCC2_PWRDN2 BSP_BIT32(13) +#define SYSCONRCC2_BYPASS2 BSP_BIT32(11) +#define SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6) +#define SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6) + uint32_t rcc2; + + uint32_t reserved_5[2]; + +#define SYSCONMOSCCTL_CVAL BSP_BIT32(0) + uint32_t moscctl; + + uint32_t reserved_6[32]; + +#define SYSCONRCGC0_PWM BSP_BIT32(20) +#define SYSCONRCGC0_ADC BSP_BIT32(16) +#define SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9) +#define SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9) +#define SYSCONRCGC0_HIB BSP_BIT32(6) +#define SYSCONRCGC0_WDT BSP_BIT32(3) + uint32_t rcgc0; + +#define SYSCONRCGC1_COMP1 BSP_BIT32(25) +#define SYSCONRCGC1_COMP0 BSP_BIT32(24) +#define SYSCONRCGC1_TIMER3 BSP_BIT32(19) +#define SYSCONRCGC1_TIMER2 BSP_BIT32(18) +#define SYSCONRCGC1_TIMER1 BSP_BIT32(17) +#define SYSCONRCGC1_TIMER0 BSP_BIT32(16) +#define SYSCONRCGC1_I2C1 BSP_BIT32(14) +#define SYSCONRCGC1_I2C0 BSP_BIT32(12) +#define SYSCONRCGC1_QEI0 BSP_BIT32(8) +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +#define SYSCONRCGC1_SSI1 BSP_BIT32(5) +#endif +#define SYSCONRCGC1_SSI0 BSP_BIT32(4) +#define SYSCONRCGC1_UART2 BSP_BIT32(2) +#define SYSCONRCGC1_UART1 BSP_BIT32(1) +#define SYSCONRCGC1_UART0 BSP_BIT32(0) + uint32_t rcgc1; + +#define SYSCONRCGC2_USB0 BSP_BIT32(16) +#define SYSCONRCGC2_UDMA BSP_BIT32(13) +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define SYSCONRCGC2_GPIOH BSP_BIT32(7) +#endif +#define SYSCONRCGC2_GPIOG BSP_BIT32(6) +#define SYSCONRCGC2_GPIOF BSP_BIT32(5) +#define SYSCONRCGC2_GPIOE BSP_BIT32(4) +#define SYSCONRCGC2_GPIOD BSP_BIT32(3) +#define SYSCONRCGC2_GPIOC BSP_BIT32(2) +#define SYSCONRCGC2_GPIOB BSP_BIT32(1) +#define SYSCONRCGC2_GPIOA BSP_BIT32(0) + uint32_t rcgc2; + + uint32_t reserved_7; + + uint32_t scgc0; + uint32_t scgc1; + uint32_t scgc2; + + uint32_t reserved_8; + + uint32_t dcgc0; + uint32_t dcgc1; + uint32_t dcgc2; + + uint32_t reserved_9[6]; + +#define SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28) +#define SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28) +#define SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6) +#define SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6) + uint32_t dslpclkcfg; +} lm3s69xx_syscon; + +typedef struct { +#define UARTDR_OE BSP_BIT32(11) +#define UARTDR_BE BSP_BIT32(10) +#define UARTDR_PE BSP_BIT32(9) +#define UARTDR_FE BSP_BIT32(8) +#define UARTDR_DATA(val) BSP_FLD32(val, 0, 7) + uint32_t dr; + + uint32_t rsr_ecr; + uint32_t reserved_0[4]; + +#define UARTFR_TXFE BSP_BIT32(7) +#define UARTFR_RXFF BSP_BIT32(6) +#define UARTFR_TXFF BSP_BIT32(5) +#define UARTFR_RXFE BSP_BIT32(4) +#define UARTFR_BUSY BSP_BIT32(3) + uint32_t fr; + + uint32_t reserved_1; + + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + +#define UARTLCRH_SPS BSP_BIT32(7) +#define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6) +#define UARTLCRH_FEN BSP_BIT32(4) +#define UARTLCRH_STP2 BSP_BIT32(3) +#define UARTLCRH_EPS BSP_BIT32(2) +#define UARTLCRH_PEN BSP_BIT32(1) +#define UARTLCRH_BRK BSP_BIT32(0) + uint32_t lcrh; + +#define UARTCTL_RXE BSP_BIT32(9) +#define UARTCTL_TXE BSP_BIT32(8) +#define UARTCTL_LBE BSP_BIT32(7) +#define UARTCTL_SIRLP BSP_BIT32(2) +#define UARTCTL_SIREN BSP_BIT32(1) +#define UARTCTL_UARTEN BSP_BIT32(0) + uint32_t ctl; + +#define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) +#define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) + uint32_t ifls; + +#define UARTI_OE BSP_BIT32(10) +#define UARTI_BE BSP_BIT32(9) +#define UARTI_PE BSP_BIT32(8) +#define UARTI_FE BSP_BIT32(7) +#define UARTI_RT BSP_BIT32(6) +#define UARTI_TX BSP_BIT32(5) +#define UARTI_RX BSP_BIT32(4) + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; +#if LM3S69XX_HAS_UDMA + uint32_t dmactl; +#endif +} lm3s69xx_uart; + +typedef struct { +#define SSICR0_SCR(val) BSP_FLD32(val, 8, 15) +#define SSICR0_SPH BSP_BIT32(7) +#define SSICR0_SPO BSP_BIT32(6) +#define SSICR0_FRF(val) BSP_FLD32(val, 4, 5) +#define SSICR0_DSS(val) BSP_FLD32(val, 0, 3) + uint32_t cr0; + +#define SSICR1_SOD BSP_BIT32(3) +#define SSICR1_MS BSP_BIT32(2) +#define SSICR1_SSE BSP_BIT32(1) +#define SSICR1_LBM BSP_BIT32(0) + uint32_t cr1; + uint32_t dr; + +#define SSISR_BSY BSP_BIT32(4) +#define SSISR_RFF BSP_BIT32(3) +#define SSISR_RNE BSP_BIT32(2) +#define SSISR_TNF BSP_BIT32(1) +#define SSISR_TFE BSP_BIT32(0) + uint32_t sr; + +#define SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7) + uint32_t cpsr; + +#define SSII_TX BSP_BIT32(3) +#define SSII_RX BSP_BIT32(2) +#define SSII_RT BSP_BIT32(1) +#define SSII_ROR BSP_BIT32(0) + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; + +#if LM3S69XX_HAS_UDMA +#define SSIDMACTL_TXDMAE BSP_BIT32(1) +#define SSIDMACTL_RXDMAE BSP_BIT32(0) + uint32_t dmactl; +#endif /* LM3S69XX_HAS_UDMA */ +} lm3s69xx_ssi; #endif /* LIBBSP_ARM_LM3S69XX_LM3S69XX_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/ssi.h b/c/src/lib/libbsp/arm/lm3s69xx/include/ssi.h new file mode 100644 index 0000000000..1089769d7d --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/include/ssi.h @@ -0,0 +1,27 @@ +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ +#ifndef LIBBSP_ARM_LM3S69XX_SSI_H +#define LIBBSP_ARM_LM3S69XX_SSI_H +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern rtems_libi2c_bus_t * const lm3s69xx_ssi_0; + +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +extern rtems_libi2c_bus_t * const lm3s69xx_ssi_1; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_SSI_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/syscon.h b/c/src/lib/libbsp/arm/lm3s69xx/include/syscon.h new file mode 100644 index 0000000000..0f3dc3b0cf --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/include/syscon.h @@ -0,0 +1,26 @@ +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ +#ifndef LIBBSP_ARM_LM3S69XX_SYSCON_H +#define LIBBSP_ARM_LM3S69XX_SYSCON_H +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_pwm_clock(bool enable); +void lm3s69xx_syscon_set_pwmdiv(unsigned int div); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_SYSCON_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/uart.h b/c/src/lib/libbsp/arm/lm3s69xx/include/uart.h index bb68090c28..bc7f921ce0 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/uart.h +++ b/c/src/lib/libbsp/arm/lm3s69xx/include/uart.h @@ -16,67 +16,11 @@ #define LIBBSP_ARM_LM3S69XX_UART_H #include -#include #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ -typedef struct { -#define UARTDR_OE BSP_BIT32(11) -#define UARTDR_BE BSP_BIT32(10) -#define UARTDR_PE BSP_BIT32(9) -#define UARTDR_FE BSP_BIT32(8) -#define UARTDR_DATA(val) BSP_FLD32(val, 0, 7) - uint32_t dr; - - uint32_t rsr_ecr; - uint32_t reserved [4]; - -#define UARTFR_TXFE BSP_BIT32(7) -#define UARTFR_RXFF BSP_BIT32(6) -#define UARTFR_TXFF BSP_BIT32(5) -#define UARTFR_RXFE BSP_BIT32(4) -#define UARTFR_BUSY BSP_BIT32(3) - uint32_t fr; - uint32_t ilpr; - uint32_t ibrd; - uint32_t fbrd; - -#define UARTLCRH_SPS BSP_BIT32(7) -#define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6) -#define UARTLCRH_FEN BSP_BIT32(4) -#define UARTLCRH_STP2 BSP_BIT32(3) -#define UARTLCRH_EPS BSP_BIT32(2) -#define UARTLCRH_PEN BSP_BIT32(1) -#define UARTLCRH_BRK BSP_BIT32(0) - uint32_t lcrh; - -#define UARTCTL_RXE BSP_BIT32(9) -#define UARTCTL_TXE BSP_BIT32(8) -#define UARTCTL_LBE BSP_BIT32(7) -#define UARTCTL_SIRLP BSP_BIT32(2) -#define UARTCTL_SIREN BSP_BIT32(1) -#define UARTCTL_UARTEN BSP_BIT32(0) - uint32_t ctl; - -#define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) -#define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) - uint32_t ifls; - -#define UARTI_OE BSP_BIT32(10) -#define UARTI_BE BSP_BIT32(9) -#define UARTI_PE BSP_BIT32(8) -#define UARTI_FE BSP_BIT32(7) -#define UARTI_RT BSP_BIT32(6) -#define UARTI_TX BSP_BIT32(5) -#define UARTI_RX BSP_BIT32(4) - uint32_t im; - uint32_t ris; - uint32_t mis; - uint32_t icr; -} lm3s69xx_uart; - extern const console_fns lm3s69xx_uart_fns; #ifdef __cplusplus diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749.cfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749.cfg new file mode 100644 index 0000000000..c9edf2baf6 --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749.cfg @@ -0,0 +1,5 @@ +# +# Config file for LM3S3749. +# + +include $(RTEMS_ROOT)/make/custom/lm3s69xx.inc diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965_qemu.cfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965_qemu.cfg new file mode 100644 index 0000000000..0ef2615af6 --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965_qemu.cfg @@ -0,0 +1,5 @@ +# +# Config file for QEMU LM3S6965 emulation. +# + +include $(RTEMS_ROOT)/make/custom/lm3s69xx.inc diff --git a/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am b/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am index d2fdfd27cd..db476c2caa 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am @@ -101,6 +101,18 @@ $(PROJECT_INCLUDE)/bsp/uart.h: include/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h +$(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h + +$(PROJECT_INCLUDE)/bsp/syscon.h: include/syscon.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/syscon.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/syscon.h + +$(PROJECT_INCLUDE)/bsp/ssi.h: include/ssi.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ssi.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ssi.h + $(PROJECT_INCLUDE)/bsp/lm3s69xx.h: include/lm3s69xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lm3s69xx.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lm3s69xx.h diff --git a/c/src/lib/libbsp/arm/lm3s69xx/ssi/ssi.c b/c/src/lib/libbsp/arm/lm3s69xx/ssi/ssi.c new file mode 100644 index 0000000000..d5f3d17eb3 --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/ssi/ssi.c @@ -0,0 +1,170 @@ +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include +#include +#include +#include +#include +#include + +typedef struct { + rtems_libi2c_bus_t bus; + volatile lm3s69xx_ssi *regs; + int bus_number; + uint16_t idle_char; + uint8_t cs_pin; + lm3s69xx_gpio_config io_configs[3]; +} lm3s69xx_ssi_bus_entry; + +static rtems_status_code lm3s69xx_ssi_init(rtems_libi2c_bus_t *bus) +{ + lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; + volatile lm3s69xx_ssi* regs = e->regs; + uint32_t clock_div = LM3S69XX_SYSTEM_CLOCK / 2 / LM3S69XX_SSI_CLOCK; + + lm3s69xx_gpio_set_config_array(e->io_configs, 3); + + lm3s69xx_syscon_enable_ssi_clock(e->bus_number, true); + regs->cr1 = 0; + regs->cpsr = SSI_CPSRDIV(2); + regs->cr0 = SSICR0_SCR(clock_div - 1) | SSICR0_SPO | SSICR0_SPH | SSICR0_FRF(0) | SSICR0_DSS(7); + regs->cr1 = SSICR1_SSE; + + return RTEMS_SUCCESSFUL; +} + +static rtems_status_code lm3s69xx_ssi_send_start(rtems_libi2c_bus_t *bus) +{ + return RTEMS_SUCCESSFUL; +} + +static rtems_status_code lm3s69xx_ssi_send_stop(rtems_libi2c_bus_t *bus) +{ + lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; + volatile lm3s69xx_ssi* regs = e->regs; + + while ((regs->sr & SSISR_BSY) != 0) + /* wait */; + + lm3s69xx_gpio_set_pin(e->cs_pin, true); + + return RTEMS_SUCCESSFUL; +} + +static rtems_status_code lm3s69xx_ssi_send_addr(rtems_libi2c_bus_t *bus, + uint32_t addr, int rw) +{ + lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; + e->cs_pin = addr; + lm3s69xx_gpio_set_pin(e->cs_pin, false); + + return RTEMS_SUCCESSFUL; +} + +static int lm3s69xx_ssi_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n) +{ + lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; + volatile lm3s69xx_ssi* regs = e->regs; + int i; + + for (i = 0; i < n; i++) { + while ((regs->sr & SSISR_TNF) == 0) + /* wait */; + + regs->dr = e->idle_char; + + while ((regs->sr & SSISR_RNE) == 0) + /* wait */; + + in[i] = regs->dr & 0xff; + } + + return n; +} + +static int lm3s69xx_ssi_write(rtems_libi2c_bus_t *bus, unsigned char *out, int n) +{ + lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; + volatile lm3s69xx_ssi* regs = e->regs; + int i; + + for (i = 0; i < n; i++) { + while ((regs->sr & SSISR_TNF) == 0) + /* wait */; + + regs->dr = out[i]; + + while ((regs->sr & SSISR_RNE) == 0) + /* wait */; + + uint32_t dummy = regs->dr; + (void)dummy; + } + + return n; +} + +static int lm3s69xx_ssi_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg) +{ + return -RTEMS_NOT_DEFINED; +} + +static const rtems_libi2c_bus_ops_t lm3s69xx_ssi_ops = { + .init = lm3s69xx_ssi_init, + .send_start = lm3s69xx_ssi_send_start, + .send_stop = lm3s69xx_ssi_send_stop, + .send_addr = lm3s69xx_ssi_send_addr, + .read_bytes = lm3s69xx_ssi_read, + .write_bytes = lm3s69xx_ssi_write, + .ioctl = lm3s69xx_ssi_ioctl +}; + +static lm3s69xx_ssi_bus_entry ssi_0_bus = { + .bus = { + .ops = &lm3s69xx_ssi_ops, + .size = sizeof(lm3s69xx_ssi_bus_entry) + }, + .regs = (volatile lm3s69xx_ssi *)LM3S69XX_SSI_0_BASE, + .bus_number = 0, + .idle_char = 0xffff, + .io_configs = { +#if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965) + LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_A, 2), /* CLK */ + LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_A, 5), /* TX */ + LM3S69XX_PIN_SSI_RX(LM3S69XX_PORT_A, 4) /* RX */ +#else +#error No GPIO pin definitions for SSI 0 +#endif + } +}; + +rtems_libi2c_bus_t * const lm3s69xx_ssi_0 = &ssi_0_bus.bus; + +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +static lm3s69xx_ssi_bus_entry ssi_1_bus = { + .bus = { + .ops = &lm3s69xx_ssi_ops, + .size = sizeof(lm3s69xx_ssi_bus_entry) + }, + .regs = (volatile lm3s69xx_ssi *)LM3S69XX_SSI_1_BASE, + .bus_number = 1, + .idle_char = 0xffff, + .io_configs = { +#if defined(LM3S69XX_MCU_LM3S3749) + LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_E, 0), /* CLK */ + LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_E, 3), /* TX */ + LM3S69XX_PIN_SSI_RX(LM3S69XX_PORT_E, 2) /* RX */ +#else +#error No GPIO pin definitions for SSI 1 +#endif + } +}; + +rtems_libi2c_bus_t * const lm3s69xx_ssi_1 = &ssi_1_bus.bus; +#endif /* LM3S69XX_NUM_SSI_BLOCKS > 1 */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/bspreset.c b/c/src/lib/libbsp/arm/lm3s69xx/startup/bspreset.c index 686f5a4263..afebd0c71c 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/startup/bspreset.c +++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/bspreset.c @@ -1,4 +1,6 @@ /* + * Copyright © 2013 Eugeniy Meshcheryakov + * * Copyright (c) 2011 Sebastian Huber. All rights reserved. * * embedded brains GmbH @@ -24,5 +26,9 @@ void bsp_reset(void) rtems_interrupt_disable(level); - _ARMV7M_NVIC->reserved_5 [0] = 0; + _ARMV7M_SCB->aircr = ARMV7M_SCB_AIRCR_VECTKEY + | ARMV7M_SCB_AIRCR_SYSRESETREQ; + + while (true) + /* Do nothing */; } diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c b/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c index a8b54f209c..23a04a5edc 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c +++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c @@ -1,11 +1,5 @@ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * + * Copyright © 2013 Eugeniy Meshcheryakov * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -13,12 +7,99 @@ */ #include -#include +#include #include -#include -#include +#include +#include +#include +#include + +static void init_main_osc(void) +{ + volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; + + uint32_t sysdiv_val = LM3S69XX_PLL_FREQUENCY / LM3S69XX_SYSTEM_CLOCK; + assert(sysdiv_val * LM3S69XX_SYSTEM_CLOCK == LM3S69XX_PLL_FREQUENCY); + assert((sysdiv_val >= 4) && (sysdiv_val <= 16)); + + uint32_t rcc = syscon->rcc; + + rcc = (rcc & ~SYSCONRCC_USESYSDIV) | SYSCONRCC_BYPASS; + syscon->rcc = rcc; + + rcc = (rcc & ~(SYSCONRCC_PWRDN | SYSCONRCC_XTAL_MSK | SYSCONRCC_OSCSRC_MSK)) + | SYSCONRCC_XTAL(LM3S69XX_XTAL_CONFIG) | SYSCONRCC_OSCSRC_MOSC; + syscon->rcc = rcc; + + rcc = (rcc & ~SYSCONRCC_SYSDIV_MSK) | SYSCONRCC_SYSDIV(sysdiv_val / 2 - 1) + | SYSCONRCC_USESYSDIV; + syscon->rcc = rcc; + + while ((syscon->ris & SYSCONRIS_PLLLRIS) == 0) + /* Wait for PLL lock */; + + rcc &= ~SYSCONRCC_BYPASS; + syscon->rcc = rcc; +} + +static const lm3s69xx_gpio_config start_config_gpio[] = { +#ifdef LM3S69XX_ENABLE_UART_0 +#if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965) + LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_A, 0), + LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_A, 1), +#else +#error No GPIO pin configuration for UART 0 +#endif +#endif /* LM3S69XX_ENABLE_UART_0 */ + +#ifdef LM3S69XX_ENABLE_UART_1 +#if defined(LM3S69XX_MCU_LM3S3749) + LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_B, 0), + LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_B, 1), +#elif defined(LM3S69XX_MCU_LM3S6965) + LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_D, 2); + LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_D, 3); +#else +#error No GPIO pin configuration for UART 1 +#endif +#endif /* LM3S69XX_ENABLE_UART_1 */ + +#ifdef LM3S69XX_ENABLE_UART_2 +#if defined(LM3S69XX_MCU_LM3S3749) + LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_D, 0), + LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_D, 1), +#elif defined(LM3S69XX_MCU_LM3S6965) + LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_G, 0), + LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_G, 1), +#else +#error No GPIO pin configuration for UART 2 +#endif +#endif /* LM3S69XX_ENABLE_UART_2 */ +}; + +static void init_gpio(void) +{ +#if LM3S69XX_USE_AHB_FOR_GPIO + volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; + + syscon->gpiohbctl |= SYSCONGPIOHBCTL_PORTA | SYSCONGPIOHBCTL_PORTB + | SYSCONGPIOHBCTL_PORTC | SYSCONGPIOHBCTL_PORTD + | SYSCONGPIOHBCTL_PORTE | SYSCONGPIOHBCTL_PORTF + | SYSCONGPIOHBCTL_PORTG +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 + | SYSCONGPIOHBCTL_PORTH +#endif + ; + +#endif /* LM3S69XX_USE_AHB_FOR_GPIO */ + + lm3s69xx_gpio_set_config_array(start_config_gpio, + sizeof(start_config_gpio) / sizeof(start_config_gpio[0])); +} void bsp_start(void) { + init_main_osc(); + init_gpio(); bsp_interrupt_initialize(); } diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/io.c b/c/src/lib/libbsp/arm/lm3s69xx/startup/io.c new file mode 100644 index 0000000000..a84dbf508a --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/io.c @@ -0,0 +1,144 @@ +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include +#include +#include +#include + +static void set_bit(volatile uint32_t *reg, unsigned index, uint32_t set) +{ + uint32_t mask = 1U; + uint32_t val = *reg; + + val &= ~(mask << index); + val |= set << index; + + *reg = val; +} + +static void set_config(unsigned int pin, const lm3s69xx_gpio_config *config) +{ + unsigned int port = LM3S69XX_GPIO_PORT_OF_PIN(pin); + volatile lm3s69xx_gpio *gpio = LM3S69XX_GPIO(port); + unsigned int index = LM3S69XX_GPIO_INDEX_OF_PIN(pin); + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + + lm3s69xx_syscon_enable_gpio_clock(port, true); + + /* Disable digital and analog functions before reconfiguration. */ + set_bit(&gpio->den, index, 0); + set_bit(&gpio->amsel, index, 0); + + set_bit(&gpio->afsel, index, config->alternate); + set_bit(&gpio->dir, index, config->dir); + set_bit(&gpio->odr, index, config->otype); + + switch (config->drive) { + case LM3S69XX_GPIO_DRIVE_4MA: + gpio->dr4r |= 1 << index; + break; + case LM3S69XX_GPIO_DRIVE_8MA: + gpio->dr8r |= 1 << index; + break; + default: + gpio->dr2r |= 1 << index; + break; + } + + switch (config->pull) { + case LM3S69XX_GPIO_PULL_UP: + gpio->pur |= 1 << index; + break; + case LM3S69XX_GPIO_PULL_DOWN: + gpio->pdr |= 1 << index; + break; + default: + set_bit(&gpio->pdr, index, 0); + set_bit(&gpio->pur, index, 0); + break; + } + + set_bit(&gpio->slr, index, config->slr); + + set_bit(&gpio->den, index, config->digital); + set_bit(&gpio->amsel, index, config->analog); + + rtems_interrupt_enable(level); +} + +void lm3s69xx_gpio_set_config(const lm3s69xx_gpio_config *config) +{ + unsigned int current = config->pin_first; + unsigned int last = config->pin_last; + + while (current <= last) { + set_config(current, config); + current++; + } +} + +void lm3s69xx_gpio_set_config_array(const lm3s69xx_gpio_config *configs, unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + lm3s69xx_gpio_set_config(&configs[i]); +} + +/** + * Enables/disables digital function on the specified pin. + */ +void lm3s69xx_gpio_digital_enable(unsigned int pin, bool enable) +{ + unsigned int port = LM3S69XX_GPIO_PORT_OF_PIN(pin); + volatile lm3s69xx_gpio *gpio = LM3S69XX_GPIO(port); + unsigned int index = LM3S69XX_GPIO_INDEX_OF_PIN(pin); + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + set_bit(&gpio->den, index, enable); + rtems_interrupt_enable(level); +} + +/** + * Enables/disables analog mode on the specified pin. + */ +void lm3s69xx_gpio_analog_mode_select(unsigned int pin, bool enable) +{ + unsigned int port = LM3S69XX_GPIO_PORT_OF_PIN(pin); + volatile lm3s69xx_gpio *gpio = LM3S69XX_GPIO(port); + unsigned int index = LM3S69XX_GPIO_INDEX_OF_PIN(pin); + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + set_bit(&gpio->amsel, index, enable); + rtems_interrupt_enable(level); +} + +void lm3s69xx_gpio_set_pin(unsigned int pin, bool set) +{ + unsigned int port = LM3S69XX_GPIO_PORT_OF_PIN(pin); + volatile lm3s69xx_gpio *gpio = LM3S69XX_GPIO(port); + unsigned int index = LM3S69XX_GPIO_INDEX_OF_PIN(pin); + uint32_t mask = 1U << index; + + gpio->data[mask] = set ? mask : 0; +} + +bool lm3s69xx_gpio_get_pin(unsigned int pin) +{ + unsigned int port = LM3S69XX_GPIO_PORT_OF_PIN(pin); + volatile lm3s69xx_gpio *gpio = LM3S69XX_GPIO(port); + unsigned int index = LM3S69XX_GPIO_INDEX_OF_PIN(pin); + uint32_t mask = 1U << index; + + return gpio->data[mask] != 0; +} diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s3749 b/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s3749 new file mode 100644 index 0000000000..acfddc72e2 --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s3749 @@ -0,0 +1,28 @@ +/** + * @file + * + * @brief Memory map. + */ + +MEMORY { + RAM_INT (AIW) : ORIGIN = 0x20000000, LENGTH = 64K + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 128K +} + +REGION_ALIAS ("REGION_START", ROM_INT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", ROM_INT); +REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_RODATA", ROM_INT); +REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_DATA", RAM_INT); +REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_BSS", RAM_INT); +REGION_ALIAS ("REGION_WORK", RAM_INT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +INCLUDE linkcmds.armv7m diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965 b/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965 index 72c06a8c7c..573c9ffa5a 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965 +++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965 @@ -5,8 +5,8 @@ */ MEMORY { - RAM_INT (AIW) : ORIGIN = 0x20000000, LENGTH = 16M - ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 64M + RAM_INT (AIW) : ORIGIN = 0x20000000, LENGTH = 64K + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 256K } REGION_ALIAS ("REGION_START", ROM_INT); diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965_qemu b/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965_qemu new file mode 100644 index 0000000000..72c06a8c7c --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965_qemu @@ -0,0 +1,28 @@ +/** + * @file + * + * @brief Memory map. + */ + +MEMORY { + RAM_INT (AIW) : ORIGIN = 0x20000000, LENGTH = 16M + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 64M +} + +REGION_ALIAS ("REGION_START", ROM_INT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", ROM_INT); +REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_RODATA", ROM_INT); +REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_DATA", RAM_INT); +REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_BSS", RAM_INT); +REGION_ALIAS ("REGION_WORK", RAM_INT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +INCLUDE linkcmds.armv7m diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/syscon.c b/c/src/lib/libbsp/arm/lm3s69xx/startup/syscon.c new file mode 100644 index 0000000000..463bfd7d51 --- /dev/null +++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/syscon.c @@ -0,0 +1,106 @@ +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include +#include +#include + +static void delay_3_clocks(void) +{ + asm volatile( + "nop\n\t" + "nop\n\t" + "nop"); +} + +void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable) +{ + volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; + uint32_t mask = 1 << port; + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + + if (enable) + syscon->rcgc2 |= mask; + else + syscon->rcgc2 &= ~mask; + + delay_3_clocks(); + + rtems_interrupt_enable(level); +} + +void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable) +{ + volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; + uint32_t mask = 1 << port; + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + + if (enable) + syscon->rcgc1 |= mask; + else + syscon->rcgc1 &= ~mask; + + delay_3_clocks(); + + rtems_interrupt_enable(level); +} + +void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable) +{ + volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; + uint32_t mask = 1 << (port + 4); + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + + if (enable) + syscon->rcgc1 |= mask; + else + syscon->rcgc1 &= ~mask; + + delay_3_clocks(); + + rtems_interrupt_enable(level); +} + +void lm3s69xx_syscon_enable_pwm_clock(bool enable) +{ + volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + + if (enable) + syscon->rcgc0 |= SYSCONRCGC0_PWM; + else + syscon->rcgc0 &= ~SYSCONRCGC0_PWM; + + delay_3_clocks(); + + rtems_interrupt_enable(level); +} + +/** + * Sets PWMDIV field in the RCC register. + * + * @note div should be one of SCRCC_PWMDIV_DIV?_VAL constants. + */ +void lm3s69xx_syscon_set_pwmdiv(unsigned int div) +{ + volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + syscon->rcc = (syscon->rcc & ~SYSCONRCC_PWMDIV_MSK) | SYSCONRCC_PWMDIV(div) + | SYSCONRCC_USEPWMDIV; + rtems_interrupt_enable(level); +} -- cgit v1.2.3