From dffc08c0e9e0fdaa2911edf8b5067298ba468ed8 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 28 Jun 2018 13:55:29 +0200 Subject: riscv: Fix interrupt save/restore Update #3433. --- cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index 0bdfa2f481..cc47bbb7c1 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -80,7 +80,7 @@ SYM(ISR_Handler): SREG x26, (26 * CPU_SIZEOF_POINTER)(sp) SREG x27, (27 * CPU_SIZEOF_POINTER)(sp) SREG x28, (28 * CPU_SIZEOF_POINTER)(sp) - SREG x29, (28 * CPU_SIZEOF_POINTER)(sp) + SREG x29, (29 * CPU_SIZEOF_POINTER)(sp) SREG x30, (30 * CPU_SIZEOF_POINTER)(sp) SREG x31, (31 * CPU_SIZEOF_POINTER)(sp) -- cgit v1.2.3