From c7e77ee488a547e5a89d9d9f54fa6e016f3a554b Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 14 Oct 2014 12:39:57 -0500 Subject: mcf5282: Move cache to libcpu and update av5282 and uC5282 BSPs --- c/src/lib/libbsp/m68k/av5282/Makefile.am | 1 + c/src/lib/libbsp/m68k/av5282/startup/bspstart.c | 118 +++------------------ c/src/lib/libbsp/m68k/uC5282/Makefile.am | 1 + c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c | 130 ++++-------------------- c/src/lib/libcpu/m68k/Makefile.am | 5 + c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c | 122 ++++++++++++++++++++++ c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h | 6 ++ 7 files changed, 169 insertions(+), 214 deletions(-) create mode 100644 c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c diff --git a/c/src/lib/libbsp/m68k/av5282/Makefile.am b/c/src/lib/libbsp/m68k/av5282/Makefile.am index 3c37eda2cf..29993f0558 100644 --- a/c/src/lib/libbsp/m68k/av5282/Makefile.am +++ b/c/src/lib/libbsp/m68k/av5282/Makefile.am @@ -50,6 +50,7 @@ endif libbsp_a_LIBADD = \ ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \ + ../../../libcpu/@RTEMS_CPU@/mcf5282/cachepd.rel \ ../../../libcpu/@RTEMS_CPU@/shared/misc.rel if HAS_NETWORKING libbsp_a_LIBADD += network.rel diff --git a/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c index e85ea4c53b..c2dd362a6d 100644 --- a/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c @@ -27,106 +27,6 @@ #define FLASH_BASE 0xFF800000 #define FLASH_SIZE (8*1024*1024) -/* - * CPU-space access - */ -#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) -#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) - -/* - * Read/write copy of common cache - * Split I/D cache - * Allow CPUSHL to invalidate a cache line - * Enable buffered writes - * No burst transfers on non-cacheable accesses - * Default cache mode is *disabled* (cache only ACRx areas) - */ -static uint32_t cacr_mode = MCF5XXX_CACR_CENB | - MCF5XXX_CACR_DBWE | - MCF5XXX_CACR_DCM; -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} - -/* - * Write-through data cache -- flushes are unnecessary - */ -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_flush_entire_data(void) {} - -void _CPU_cache_enable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); -} - -void _CPU_cache_invalidate_1_instruction_line(const void *addr) -{ - /* - * Top half of cache is I-space - */ - addr = (void *)((int)addr | 0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} - -void _CPU_cache_enable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_data(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); -} - -void _CPU_cache_invalidate_1_data_line(const void *addr) -{ - /* - * Bottom half of cache is D-space - */ - addr = (void *)((int)addr & ~0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} - void bsp_start( void ) { /* @@ -139,16 +39,22 @@ void bsp_start( void ) /* * Cache SDRAM and FLASH */ - m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE) | - MCF5XXX_ACR_AM(SDRAM_SIZE-1) | - MCF5XXX_ACR_EN | - MCF5XXX_ACR_BWE | - MCF5XXX_ACR_SM_IGNORE); + m68k_set_acr0( + MCF5XXX_ACR_AB(SDRAM_BASE) | + MCF5XXX_ACR_AM(SDRAM_SIZE-1) | + MCF5XXX_ACR_EN | + MCF5XXX_ACR_BWE | + MCF5XXX_ACR_SM_IGNORE + ); /* * Enable the cache */ - m68k_set_cacr(cacr_mode); + mcf5xxx_initialize_cacr( + MCF5XXX_CACR_CENB | + MCF5XXX_CACR_DBWE | + MCF5XXX_CACR_DCM + ); } extern char _CPUClockSpeed[]; diff --git a/c/src/lib/libbsp/m68k/uC5282/Makefile.am b/c/src/lib/libbsp/m68k/uC5282/Makefile.am index 6fe5787297..a77785b106 100644 --- a/c/src/lib/libbsp/m68k/uC5282/Makefile.am +++ b/c/src/lib/libbsp/m68k/uC5282/Makefile.am @@ -48,6 +48,7 @@ network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \ + ../../../libcpu/@RTEMS_CPU@/mcf5282/cachepd.rel \ ../../../libcpu/@RTEMS_CPU@/shared/misc.rel if HAS_NETWORKING libbsp_a_LIBADD += network.rel diff --git a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c index 791913d6a5..61444d7a6e 100644 --- a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @@ -36,6 +36,7 @@ extern char _PLLRefClockSpeed[]; uint32_t BSP_sys_clk_speed = (uint32_t)_CPUClockSpeed; uint32_t BSP_pll_ref_clock = (uint32_t)_PLLRefClockSpeed; + /* * CPU-space access * The NOP after writing the CACR is there to address the following issue as @@ -76,115 +77,17 @@ uint32_t BSP_pll_ref_clock = (uint32_t)_PLLRefClockSpeed; * ACRn[5] = BUFW (buffered write enable) must be 0 * Fix plan: Currently, there are no plans to fix this. */ -#define m68k_set_cacr_nop(_cacr) __asm__ volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) -#define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr)) -#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) -#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) +#define m68k_set_cacr_nop(_cacr) \ + __asm__ volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) +#define m68k_set_cacr(_cacr) \ + __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr)) +#define m68k_set_acr0(_acr0) \ + __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) +#define m68k_set_acr1(_acr1) \ + __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) -/* - * Read/write copy of cache registers - * Split instruction/data or instruction-only - * Allow CPUSHL to invalidate a cache line - * Disable buffered writes - * No burst transfers on non-cacheable accesses - * Default cache mode is *disabled* (cache only ACRx areas) - */ -uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB | -#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE - MCF5XXX_CACR_DISD | -#endif - MCF5XXX_CACR_DCM; uint32_t mcf5282_acr0_mode = 0; uint32_t mcf5282_acr1_mode = 0; -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} - -/* - * Write-through data cache -- flushes are unnecessary - */ -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_flush_entire_data(void) {} - -void _CPU_cache_enable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI; - m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI; - m68k_set_cacr(mcf5282_cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); -} - -void _CPU_cache_invalidate_1_instruction_line(const void *addr) -{ - /* - * Top half of cache is I-space - */ - addr = (void *)((int)addr | 0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} - -void _CPU_cache_enable_data(void) -{ -#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD; - m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); - rtems_interrupt_enable(level); -#endif -} - -void _CPU_cache_disable_data(void) -{ -#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - mcf5282_cacr_mode |= MCF5XXX_CACR_DISD; - m68k_set_cacr(mcf5282_cacr_mode); - rtems_interrupt_enable(level); -#endif -} - -void _CPU_cache_invalidate_entire_data(void) -{ -#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE - m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); -#endif -} - -void _CPU_cache_invalidate_1_data_line(const void *addr) -{ -#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE - /* - * Bottom half of cache is D-space - */ - addr = (void *)((int)addr & ~0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -#endif -} extern void bsp_fake_syscall(int); @@ -280,9 +183,20 @@ void bsp_start( void ) *((void (**)(int))((32+2) * 4)) = bsp_fake_syscall; /* - * Enable the cache + * Read/write copy of cache registers + * Split instruction/data or instruction-only + * Allow CPUSHL to invalidate a cache line + * Disable buffered writes + * No burst transfers on non-cacheable accesses + * Default cache mode is *disabled* (cache only ACRx areas) */ - m68k_set_cacr(mcf5282_cacr_mode); + mcf5xxx_initialize_cacr( + MCF5XXX_CACR_CENB | + #ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE + MCF5XXX_CACR_DISD | + #endif + MCF5XXX_CACR_DCM + ); /* * Set up CS* space (fake 'VME') diff --git a/c/src/lib/libcpu/m68k/Makefile.am b/c/src/lib/libcpu/m68k/Makefile.am index 2c46834347..19f500f1e1 100644 --- a/c/src/lib/libcpu/m68k/Makefile.am +++ b/c/src/lib/libcpu/m68k/Makefile.am @@ -176,6 +176,11 @@ if mcf5282 ## mcf5282/include include_mcf5282dir = $(includedir)/mcf5282 include_mcf5282_HEADERS = mcf5282/include/mcf5282.h + +noinst_PROGRAMS += mcf5282/cachepd.rel +mcf5282_cachepd_rel_SOURCES = mcf5282/cache/cachepd.c +mcf5282_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache +mcf5282_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif if mcf548x diff --git a/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c new file mode 100644 index 0000000000..e59f213236 --- /dev/null +++ b/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c @@ -0,0 +1,122 @@ +/** + * @file + * + * Cache Management Support Routines for the MCF5282 + */ + +#include +#include /* internal MCF5282 modules */ +#include "cache_.h" + +/* + * CPU-space access + */ +#define m68k_set_acr0(_acr0) \ + __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) +#define m68k_set_acr1(_acr1) \ + __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) + +#define NOP __asm__ volatile ("nop"); + +/* + * DEFAULT WHEN mcf5xxx_initialize_cacr not called + * Read/write copy of common cache + * Split I/D cache + * Allow CPUSHL to invalidate a cache line + * Enable buffered writes + * No burst transfers on non-cacheable accesses + * Default cache mode is *disabled* (cache only ACRx areas) + */ +static uint32_t cacr_mode = MCF5XXX_CACR_CENB | + MCF5XXX_CACR_DBWE | + MCF5XXX_CACR_DCM; + +void mcf5xxx_initialize_cacr(uint32_t cacr) +{ + cacr_mode = cacr; + m68k_set_cacr( cacr_mode ); +} + +/* + * Cannot be frozen + */ +void _CPU_cache_freeze_data(void) {} +void _CPU_cache_unfreeze_data(void) {} +void _CPU_cache_freeze_instruction(void) {} +void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +void _CPU_cache_flush_1_data_line(const void *d_addr) {} +void _CPU_cache_flush_entire_data(void) {} + +void _CPU_cache_enable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI ); + NOP; + rtems_interrupt_enable(level); +} + +void _CPU_cache_disable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_invalidate_entire_instruction(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); + NOP; +} + +void _CPU_cache_invalidate_1_instruction_line(const void *addr) +{ + /* + * Top half of cache is I-space + */ + addr = (void *)((int)addr | 0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} + +void _CPU_cache_enable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); + rtems_interrupt_enable(level); +} + +void _CPU_cache_disable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_invalidate_entire_data(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); +} + +void _CPU_cache_invalidate_1_data_line(const void *addr) +{ + /* + * Bottom half of cache is D-space + */ + addr = (void *)((int)addr & ~0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} diff --git a/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h b/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h index afe444cd86..3724f489de 100644 --- a/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h +++ b/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h @@ -73,6 +73,12 @@ typedef volatile uint32 vuint32 __attribute__((__may_alias__)); /* 32 bits */ #define MCF5XXX_SR_V (0x0002) #define MCF5XXX_SR_C (0x0001) +/* + * Used to set the initialize the cacr register to the BSP's desired + * starting value. + */ +void mcf5xxx_initialize_cacr(uint32_t); + #define MCF5XXX_CACR_CENB (0x80000000) #define MCF5XXX_CACR_CPDI (0x10000000) #define MCF5XXX_CACR_CPD (0x10000000) -- cgit v1.2.3