From b9cc5aa9d32c9c866db7078d12f59f5f5638c9f3 Mon Sep 17 00:00:00 2001 From: Christian Mauderer Date: Mon, 22 Aug 2016 10:41:33 +0200 Subject: bsp/atsam: Add SDRAM IS42S16320F-7BL. --- c/src/lib/libbsp/arm/atsam/README | 4 +++ c/src/lib/libbsp/arm/atsam/configure.ac | 12 ++++++- c/src/lib/libbsp/arm/atsam/startup/sdram-config.c | 41 +++++++++++++++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/c/src/lib/libbsp/arm/atsam/README b/c/src/lib/libbsp/arm/atsam/README index 3df2c017cd..5f53d5f5e9 100644 --- a/c/src/lib/libbsp/arm/atsam/README +++ b/c/src/lib/libbsp/arm/atsam/README @@ -10,6 +10,10 @@ sams70q19, sams70q20, sams70q21, samv71j19, samv71j20, samv71j21, samv71n19, samv71n20, samv71n21, samv71q19, samv71q20 and samv71q21. By default the BSP uses the ATSAMV71Q21 chip. Not all variants are tested. +Use --enable-sdram=XYZ to select the SDRAM variant where XYZ is one of +is42s16100e-7bli and is42s16320f-7bl. Not all variants are tested with all +controller and speed combinations. + Use BOARD_MAINOSC=XYZ to set the main oscillator frequency in Hz (default 12MHz). diff --git a/c/src/lib/libbsp/arm/atsam/configure.ac b/c/src/lib/libbsp/arm/atsam/configure.ac index 1297367b1c..d2c8bc0924 100644 --- a/c/src/lib/libbsp/arm/atsam/configure.ac +++ b/c/src/lib/libbsp/arm/atsam/configure.ac @@ -50,6 +50,16 @@ AC_ARG_ENABLE( esac], [AC_DEFINE([__SAMV71Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000]) +AC_ARG_ENABLE( +[sdram], +[AS_HELP_STRING([--enable-sdram],[select a SDRAM variant (default is42s16100e-7bli)])], +[case "${enableval}" in + is42s16100e-7bli) AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000 ;; + is42s16320f-7bl) AC_DEFINE([ATSAM_SDRAM_IS42S16320F_7BL],[1],[SDRAM variant]) EXTSDRAM=0x04000000 ;; + *) AC_MSG_ERROR([bad value ${enableval} for SDRAM variant]) ;; +esac], +[AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000]) + RTEMS_BSPOPTS_SET([BOARD_MAINOSC],[*],[12000000]) RTEMS_BSPOPTS_HELP([BOARD_MAINOSC],[Main oscillator frequency in Hz (default 12MHz)]) @@ -76,7 +86,7 @@ AC_ARG_VAR([$1],[$2])dnl ATSAM_LINKCMD([ATSAM_MEMORY_TCM_SIZE],[size of tightly coupled memories (TCM) in bytes],[0x00000000]) ATSAM_LINKCMD([ATSAM_MEMORY_INTFLASH_SIZE],[size of internal flash in bytes],[${INTFLASH}]) ATSAM_LINKCMD([ATSAM_MEMORY_INTSRAM_SIZE],[size of internal SRAM in bytes],[${INTSRAM}]) -ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in bytes],[0x00200000]) +ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in bytes],[${EXTSDRAM}]) ATSAM_LINKCMD([ATSAM_MEMORY_QSPIFLASH_SIZE],[size of QSPI flash in bytes],[0x00200000]) AC_CONFIG_FILES([ diff --git a/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c b/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c index 65060a73f7..51c8f02034 100644 --- a/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c +++ b/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c @@ -12,10 +12,13 @@ * http://www.rtems.org/license/LICENSE. */ +#include #include #include +#if defined ATSAM_SDRAM_IS42S16100E_7BLI const struct BOARD_Sdram_Config BOARD_Sdram_Config = { + /* FIXME: a lot of these values should be calculated using CPU frequency */ .sdramc_tr = 1562, .sdramc_cr = SDRAMC_CR_NC_COL8 /* 8 column bits */ @@ -32,3 +35,41 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = { .sdramc_mdr = SDRAMC_MDR_MD_SDRAM, .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2) }; + +#elif defined ATSAM_SDRAM_IS42S16320F_7BL +#define CLOCK_CYCLES_FROM_NS_MAX(ns) \ + (((ns) * (BOARD_MCK / 1000ul / 1000ul)) / 1000ul) +#define CLOCK_CYCLES_FROM_NS_MIN(ns) (CLOCK_CYCLES_FROM_NS_MAX(ns) + 1) + +const struct BOARD_Sdram_Config BOARD_Sdram_Config = { + /* 8k refresh cycles every 64ms => 7.8125us */ + .sdramc_tr = CLOCK_CYCLES_FROM_NS_MAX(7812ul), + .sdramc_cr = + SDRAMC_CR_NC_COL10 + | SDRAMC_CR_NR_ROW13 + | SDRAMC_CR_CAS_LATENCY3 + | SDRAMC_CR_NB_BANK4 + | SDRAMC_CR_DBW + /* t_WR = 30ns min (t_RC - t_RP - t_RCD; + * see data sheet November 2015 page 55); + * add some security margin */ + | SDRAMC_CR_TWR(CLOCK_CYCLES_FROM_NS_MIN(40)) + | SDRAMC_CR_TRC_TRFC(CLOCK_CYCLES_FROM_NS_MIN(60)) + | SDRAMC_CR_TRP(CLOCK_CYCLES_FROM_NS_MIN(15)) + | SDRAMC_CR_TRCD(CLOCK_CYCLES_FROM_NS_MIN(15)) + | SDRAMC_CR_TRAS(CLOCK_CYCLES_FROM_NS_MIN(37)) + | SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)), + .sdramc_mdr = SDRAMC_MDR_MD_SDRAM, + .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | + SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14)) +}; + +#if CLOCK_CYCLES_FROM_NS_MIN(67) > 0xF + /* Prevent the fields to be out of range by checking the one with the biggest + * value. */ + #error SDRAM calculation does not work for the selected clock frequency +#endif + +#else + #error SDRAM not supported. +#endif -- cgit v1.2.3