From b87bf0bfc2d442b30800a9d4facca90148534430 Mon Sep 17 00:00:00 2001 From: Ralf Kirchner Date: Mon, 17 Feb 2014 11:44:47 +0100 Subject: bsp/arm: Add arm-errata.h and arm-release-id.h --- c/src/lib/libbsp/arm/shared/include/arm-errata.h | 127 +++++++++++++++++ .../lib/libbsp/arm/shared/include/arm-release-id.h | 152 +++++++++++++++++++++ 2 files changed, 279 insertions(+) create mode 100644 c/src/lib/libbsp/arm/shared/include/arm-errata.h create mode 100644 c/src/lib/libbsp/arm/shared/include/arm-release-id.h diff --git a/c/src/lib/libbsp/arm/shared/include/arm-errata.h b/c/src/lib/libbsp/arm/shared/include/arm-errata.h new file mode 100644 index 0000000000..6f26c1f708 --- /dev/null +++ b/c/src/lib/libbsp/arm/shared/include/arm-errata.h @@ -0,0 +1,127 @@ +/** + * @file arm-errata.h + * + * @ingroup arm_shared + * + * @brief Create #defines which state which erratas shall get applied + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_ERRATA_H_ +#define ARM_ERRATA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if defined( __ARM_ARCH_7A__ ) +static arm_release_id arm_errata_get_processor_release( + void +) +{ + const uint32_t MIDR = arm_cp15_get_id_code(); + const uint8_t REVISION = (MIDR & 0xF00000U) >> 20; + const uint8_t PATCH_LEVEL = (MIDR & 0xFU); + + return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( + REVISION, + PATCH_LEVEL + ); +} +#endif /* #if defined( __ARM_ARCH_7A__ ) */ + +#if defined( __ARM_ARCH_7A__ ) +static bool arm_errata_is_applicable_processor_errata_764369( + void +) +{ + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R4_P1: + case ARM_RELEASE_ID_R4_P4: + case ARM_RELEASE_ID_R3_P0: + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + case ARM_RELEASE_ID_R2_P0: + is_applicable = true; + default: + is_applicable = false; + break; + } + + return is_applicable; +} +#endif /* #if defined( __ARM_ARCH_7A__ ) */ + +#if defined( __ARM_ARCH_7A__ ) +static bool arm_errata_is_applicable_processor_errata_775420( + void +) +{ + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + is_applicable = true; + default: + is_applicable = false; + break; + } + + return is_applicable; +} +#endif /* #if defined( __ARM_ARCH_7A__ ) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_ERRATA_H_ */ \ No newline at end of file diff --git a/c/src/lib/libbsp/arm/shared/include/arm-release-id.h b/c/src/lib/libbsp/arm/shared/include/arm-release-id.h new file mode 100644 index 0000000000..e06be006da --- /dev/null +++ b/c/src/lib/libbsp/arm/shared/include/arm-release-id.h @@ -0,0 +1,152 @@ +/** + * @file arm-release-id.h + * + * @ingroup arm_shared + * + * @brief Create #defines for release IDs + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_RELEASE_ID_H_ +#define ARM_RELEASE_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* #define the IDs which identify a release. This must be done + * prior to #including bsp.h */ +#define ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( release_no, patch_level ) \ + ( ( ( ( release_no ) & 0xFFFF ) << 16 ) + ( ( patch_level ) & 0xFFFF ) ) + +typedef enum { + ARM_RELEASE_ID_R0_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 0 ), + ARM_RELEASE_ID_R0_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 1 ), + ARM_RELEASE_ID_R0_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 2 ), + ARM_RELEASE_ID_R0_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 3 ), + ARM_RELEASE_ID_R0_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 4 ), + ARM_RELEASE_ID_R0_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 5 ), + ARM_RELEASE_ID_R0_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 6 ), + ARM_RELEASE_ID_R0_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 7 ), + ARM_RELEASE_ID_R0_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 8 ), + ARM_RELEASE_ID_R0_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 9 ), + ARM_RELEASE_ID_R0_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 10 ), + ARM_RELEASE_ID_R1_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 0 ), + ARM_RELEASE_ID_R1_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 1 ), + ARM_RELEASE_ID_R1_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 2 ), + ARM_RELEASE_ID_R1_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 3 ), + ARM_RELEASE_ID_R1_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 4 ), + ARM_RELEASE_ID_R1_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 5 ), + ARM_RELEASE_ID_R1_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 6 ), + ARM_RELEASE_ID_R1_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 7 ), + ARM_RELEASE_ID_R1_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 8 ), + ARM_RELEASE_ID_R1_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 9 ), + ARM_RELEASE_ID_R1_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 10 ), + ARM_RELEASE_ID_R2_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 0 ), + ARM_RELEASE_ID_R2_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 1 ), + ARM_RELEASE_ID_R2_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 2 ), + ARM_RELEASE_ID_R2_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 3 ), + ARM_RELEASE_ID_R2_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 4 ), + ARM_RELEASE_ID_R2_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 5 ), + ARM_RELEASE_ID_R2_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 6 ), + ARM_RELEASE_ID_R2_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 7 ), + ARM_RELEASE_ID_R2_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 8 ), + ARM_RELEASE_ID_R2_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 9 ), + ARM_RELEASE_ID_R2_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 10 ), + ARM_RELEASE_ID_R3_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 0 ), + ARM_RELEASE_ID_R3_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 1 ), + ARM_RELEASE_ID_R3_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 2 ), + ARM_RELEASE_ID_R3_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 3 ), + ARM_RELEASE_ID_R3_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 4 ), + ARM_RELEASE_ID_R3_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 5 ), + ARM_RELEASE_ID_R3_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 6 ), + ARM_RELEASE_ID_R3_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 7 ), + ARM_RELEASE_ID_R3_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 8 ), + ARM_RELEASE_ID_R3_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 9 ), + ARM_RELEASE_ID_R3_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 10 ), + ARM_RELEASE_ID_R4_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 0 ), + ARM_RELEASE_ID_R4_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 1 ), + ARM_RELEASE_ID_R4_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 2 ), + ARM_RELEASE_ID_R4_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 3 ), + ARM_RELEASE_ID_R4_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 4 ), + ARM_RELEASE_ID_R4_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 5 ), + ARM_RELEASE_ID_R4_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 6 ), + ARM_RELEASE_ID_R4_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 7 ), + ARM_RELEASE_ID_R4_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 8 ), + ARM_RELEASE_ID_R4_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 9 ), + ARM_RELEASE_ID_R4_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 10 ), + ARM_RELEASE_ID_R5_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 0 ), + ARM_RELEASE_ID_R5_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 1 ), + ARM_RELEASE_ID_R5_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 2 ), + ARM_RELEASE_ID_R5_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 3 ), + ARM_RELEASE_ID_R5_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 4 ), + ARM_RELEASE_ID_R5_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 5 ), + ARM_RELEASE_ID_R5_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 6 ), + ARM_RELEASE_ID_R5_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 7 ), + ARM_RELEASE_ID_R5_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 8 ), + ARM_RELEASE_ID_R5_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 9 ), + ARM_RELEASE_ID_R5_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 10 ), + ARM_RELEASE_ID_R6_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 0 ), + ARM_RELEASE_ID_R6_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 1 ), + ARM_RELEASE_ID_R6_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 2 ), + ARM_RELEASE_ID_R6_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 3 ), + ARM_RELEASE_ID_R6_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 4 ), + ARM_RELEASE_ID_R6_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 5 ), + ARM_RELEASE_ID_R6_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 6 ), + ARM_RELEASE_ID_R6_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 7 ), + ARM_RELEASE_ID_R6_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 8 ), + ARM_RELEASE_ID_R6_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 9 ), + ARM_RELEASE_ID_R6_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 10 ), + ARM_RELEASE_ID_R7_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 0 ), + ARM_RELEASE_ID_R7_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 1 ), + ARM_RELEASE_ID_R7_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 2 ), + ARM_RELEASE_ID_R7_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 3 ), + ARM_RELEASE_ID_R7_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 4 ), + ARM_RELEASE_ID_R7_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 5 ), + ARM_RELEASE_ID_R7_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 6 ), + ARM_RELEASE_ID_R7_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 7 ), + ARM_RELEASE_ID_R7_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 8 ), + ARM_RELEASE_ID_R7_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 9 ), + ARM_RELEASE_ID_R7_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 10 ), + ARM_RELEASE_ID_R8_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 0 ), + ARM_RELEASE_ID_R8_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 1 ), + ARM_RELEASE_ID_R8_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 2 ), + ARM_RELEASE_ID_R8_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 3 ), + ARM_RELEASE_ID_R8_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 4 ), + ARM_RELEASE_ID_R8_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 5 ), + ARM_RELEASE_ID_R8_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 6 ), + ARM_RELEASE_ID_R8_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 7 ), + ARM_RELEASE_ID_R8_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 8 ), + ARM_RELEASE_ID_R8_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 9 ), + ARM_RELEASE_ID_R8_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 10 ), + ARM_RELEASE_ID_R9_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 0 ), + ARM_RELEASE_ID_R9_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 1 ), + ARM_RELEASE_ID_R9_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 2 ), + ARM_RELEASE_ID_R9_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 3 ), + ARM_RELEASE_ID_R9_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 4 ), + ARM_RELEASE_ID_R9_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 5 ), + ARM_RELEASE_ID_R9_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 6 ), + ARM_RELEASE_ID_R9_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 7 ), + ARM_RELEASE_ID_R9_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 8 ), + ARM_RELEASE_ID_R9_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 9 ), + ARM_RELEASE_ID_R9_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 10 ) +} arm_release_id; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_RELEASE_ID_H_ */ \ No newline at end of file -- cgit v1.2.3